Arm Enterprises IM-AD1 Setting up the logic module, Switch 2 Closed Switch 3 Open Switch 4 Open

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Getting Started

2.2Setting up the logic module

You must load the required peripheral controllers into the logic module FPGA to drive the interfaces. The interface module is supplied with example configurations that provide PrimeCell peripherals for supported logic modules.

The logic module can be programmed using Multi-ICE with or without the IM-AD1 fitted. If the IM-AD1 is fitted however, the manufacturer-specific download connector on the logic module is inaccessible. See the logic module user guide for detailed instructions on downloading new FPGA configurations

To download the supplied example logic module FPGA configuration using Multi-ICE:

1.Insert CONFIG link on the logic module (or IM-AD1 if fitted to logic module).

2.Connect Multi-ICE unit to J10 on the logic module (or J9 on the IM-AD1).

3.Power up the Integrator system.

4.Start the Multi-ICE server on your PC and click the Autoconfigure button.

5.If you are using an Altera logic module, LM-EP20K1000E, switch 4 of switchpack S1 must be set to the CLOSED position.

6.Browse to: Install_directory\IM-AD1\configure.

7.Double-click the progcards.exe program file.

8.The progcards program automatically detects whether the logic module is an Altera or a Xilinx module and uses the appropriate .brd file to download the configuration file.

9.After the programming has completed:

•power down the system

•remove the CONFIG link

•move the Multi-ICE connection to the core module.

10.Set the S1 switches on the logic module as follows: Switch 1 Open

Switch 2 Closed Switch 3 Open Switch 4 Open.

The logic module will now be configured with the example design.

If the IM-AD1 is not already fitted, install it on top of the logic module and the system is ready to use.

ARM DUI 0163B

Copyright © 2001-2003. All rights reserved.

2-3

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Contents Integrator/IM-AD1 User Guide Integrator/IM-AD1Conformance Notices Copyright 2001-2003. All rights reserved Chapter Introduction Integrator/IM-AD1 User GuideAppendix a Signal Descriptions Preface Intended audience Using this bookAbout this book ARM publications Typographical conventionsFurther reading Third-party documents Feedback on the Integrator/IM-AD1 FeedbackFeedback on this document Xii Introduction ARM DUI 0163B About the Integrator/IM-AD1Integrator/IM-AD1 layout Features Interface module features and architectureArchitecture Integrator/IM-AD1 block diagramLinks and LEDs Config LEDCare of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Assembled Integrator development system Fitting the interface moduleSwitch 2 Closed Switch 3 Open Switch 4 Open Setting up the logic moduleRunning the test software Hardware Reference Hardware Reference Description Serial interface signal assignment Signal nameConnector Uart interfaceSerial connector signal assignment Pin J18 Type Description Serial connector pinoutSPI SPI signals SignalPWM interface PWM interface signals SignalPWM connector signals Pin J14 J10 Description Shows the signal assignmentFunctional description Stepper motor interfaceTherefore, with a 0.1Ω sense resistor fitted Stepper motor interface signal summaryStepper motor interface signals Stepper motor connectorsVSS Stepper motor connector signals Pin J19 J23 DescriptionGpio Gpio connectors J16 and J17Hardware Reference Buffer Can interfaceU13 Can interface signal assignment Signal IMBBANK30 IMBBANK28IMBBANK29 GND Can connector signal assignments Pin10 ADC and DAC interface architecture ADC and DAC interfacesIMABANK51 IMABANK48IMABANK49 IMABANK5011shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example Example architecture About the design exampleAbout PrimeCells File Description Vhdl file descriptionsExample memory map Integrator system memory map Address assignment of logic modulesIntegrator/IM-AD1 memory map Device Address Integrator/IM-AD1 memory mapLogic module addresses Position Bits Stack Ssram StepperbGpioa GpiobOffset address Name Type Function Example APB register peripheralLogic module registers Oscillator divisor registers VDW LMOSCx registers Bits Name Access FunctionRDW Push button interrupt register Bits Name Access FunctionOscillator lock register User LEDs control registerSwitches register Uart SPICS0 SPI chip select registerSPICS2 SPICS1Synchronous serial port PWM controller Count Offset Name Access Function AddressStepper motor peripheral ContStepper x control register DIR DocountSinglestep Stepx speed register Stepx count registerRead data input register Read data output pinsAddress offset Name Access Size Function Data output set registerGpio direction control 1 bit Data directionSsram interface CAN1 Vectored interrupt controllerInterrupt sources Interrupt Interrupt source Source numberReference Design Example CANxBase Can reset control registerCanreset Can controller interfaceADC2BUSY ADC and DAC interface16 ADC and DAC interface registers AdcstatusBits Name Function Peripheral information block18 PIB entry format Signal Descriptions Expa Pin label Signal Description Table A-1 AHB signal assignmentExpb Pin label Name Description Table A-2 Expb signal descriptionExpim LM-EP20K1000E Description Table A-3 Expim signal descriptionsLabel Figure A-4 J7 pin locations Logic analyzer connectorCLK1 Table A-4 J7 connector pinout Signal PinMulti-ICE Jtag Figure A-5 Multi-ICE connector pinoutMechanical Specification Mechanical information Figure B-1 Board dimensions top viewFigure B-2 Bottom board dimensions viewed from top side DB9STRAIGHT FCI Connector referenceDB9DUAL Multi-ICE GlossarySynchronous Serial Port Gpio IndexADC Can DACLmleds Lmlock LMOSC1 Expa A-2Gpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn