Arm Enterprises IM-AD1 manual Table A-2 Expb signal description, Pin label Name Description

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Signal Descriptions

Table A-2 describes the signals on the pins labeled F[31:0], H[31:0], and J[16:0].

		Table A-2 EXPB signal description

Pin label	Name	Description

F[31:24]	Not used	-

F[23:0]	F[23:0]	Stepper motor controller signals.

H[31:29]	Not used	-

H28	SYSCLK	System clock from the logic module

H[27:0]	Not used	-

J[15:14]	Not used	-

J13	nCFGEN	Sets motherboard into configuration mode

J12	nSRST	Multi-ICE reset (open collector)

J11	Not used	-

J10	RTCK	Returned JTAG test clock

J9	Not used	-

J8	nTRST	JTAG reset

J7	TDO	JTAG test data out

J6	TDI	JTAG test data in

J5	TMS	JTAG test mode select

J4	TCK	JTAG test clock

J[3:0]	Not used	-

ARM DUI 0163B

Copyright © 2001-2003. All rights reserved.

A-5

Image 79

Contents Integrator/IM-AD1 User Guide Integrator/IM-AD1Conformance Notices Copyright 2001-2003. All rights reserved Chapter Introduction Integrator/IM-AD1 User GuideAppendix a Signal Descriptions Preface About this book Using this bookIntended audience Further reading Typographical conventionsARM publications Third-party documents Feedback on this document FeedbackFeedback on the Integrator/IM-AD1 Xii Introduction ARM DUI 0163B About the Integrator/IM-AD1Integrator/IM-AD1 layout Features Interface module features and architectureArchitecture Integrator/IM-AD1 block diagramLinks and LEDs Config LEDCare of modules Introduction Copyright 2001-2003. All rights reserved Getting Started Assembled Integrator development system Fitting the interface moduleSwitch 2 Closed Switch 3 Open Switch 4 Open Setting up the logic moduleRunning the test software Hardware Reference Hardware Reference Description Serial interface signal assignment Signal nameConnector Uart interfaceSerial connector signal assignment Pin J18 Type Description Serial connector pinoutSPI SPI signals SignalPWM interface PWM interface signals SignalPWM connector signals Pin J14 J10 Description Shows the signal assignmentFunctional description Stepper motor interfaceTherefore, with a 0.1Ω sense resistor fitted Stepper motor interface signal summaryStepper motor interface signals Stepper motor connectorsVSS Stepper motor connector signals Pin J19 J23 DescriptionGpio Gpio connectors J16 and J17Hardware Reference U13 Can interfaceBuffer Can interface signal assignment Signal IMBBANK29 IMBBANK28IMBBANK30 GND Can connector signal assignments Pin10 ADC and DAC interface architecture ADC and DAC interfacesIMABANK51 IMABANK48IMABANK49 IMABANK5011shows the pinout of the ADC interface connector J1 12 shows the pinout of the DAC interface connector J2 Hardware Reference Copyright 2001-2003. All rights reserved Reference Design Example About PrimeCells About the design exampleExample architecture File Description Vhdl file descriptionsExample memory map Integrator system memory map Address assignment of logic modulesLogic module addresses Position Bits Stack Integrator/IM-AD1 memory mapIntegrator/IM-AD1 memory map Device Address Ssram StepperbGpioa GpiobLogic module registers Example APB register peripheralOffset address Name Type Function Oscillator divisor registers RDW LMOSCx registers Bits Name Access FunctionVDW Push button interrupt register Bits Name Access FunctionOscillator lock register User LEDs control registerSwitches register Uart SPICS0 SPI chip select registerSPICS2 SPICS1Synchronous serial port PWM controller Count Offset Name Access Function AddressStepper motor peripheral ContStepper x control register Singlestep DocountDIR Stepx speed register Stepx count registerRead data input register Read data output pinsAddress offset Name Access Size Function Data output set registerGpio direction control 1 bit Data directionSsram interface CAN1 Vectored interrupt controllerInterrupt sources Interrupt Interrupt source Source numberReference Design Example CANxBase Can reset control registerCanreset Can controller interfaceADC2BUSY ADC and DAC interface16 ADC and DAC interface registers Adcstatus18 PIB entry format Peripheral information blockBits Name Function Signal Descriptions Expa Pin label Signal Description Table A-1 AHB signal assignmentExpb Pin label Name Description Table A-2 Expb signal descriptionExpim Label Table A-3 Expim signal descriptionsLM-EP20K1000E Description Figure A-4 J7 pin locations Logic analyzer connectorCLK1 Table A-4 J7 connector pinout Signal PinMulti-ICE Jtag Figure A-5 Multi-ICE connector pinoutMechanical Specification Mechanical information Figure B-1 Board dimensions top viewFigure B-2 Bottom board dimensions viewed from top side DB9DUAL Connector referenceDB9STRAIGHT FCI Multi-ICE GlossarySynchronous Serial Port Gpio IndexADC Can DACGpiodataclr Gpiodatain Gpiodataout Gpiodataset Gpiodirn Expa A-2Lmleds Lmlock LMOSC1