Motorola MVME197LE user manual List of Tables

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	List of Tables
Table 1-1. MVME197LE Specifications		1-3
Table 3-1. Processor Bus Memory Map		3-3
Table 3-2.	Local Devices Memory Map	3-4
Table 3-3.	BusSwitch Register Memory Map	3-6
Table 3-4. ECDM CSR Register Memory Map		3-7
Table 3-5. DCAM (I2C) Register Memory Map		3-8
Table 3-6. VMEchip2 Memory Map		3-9
Table 3-7. PCCchip2 Memory Map		3-13
Table 3-8.	Printer Memory Map	3-14
Table 3-9.	Cirrus Logic CD2401 Serial Port Memory Map	3-15
Table 3-10. 82596CA Ethernet LAN Memory Map		3-16
Table 3-11. 53C710 SCSI Memory Map		3-17
Table 3-12. MK48T08 BBRAM, TOD Clock Memory Map		3-17
Table 3-13. BBRAM Configuration Area Memory Map		3-18
Table 3-14. TOD Clock Memory Map		3-18
Table A-1. EIA-232-D Interconnections		A-2

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Contents MVME197LE/D2 MVME197LERestricted Rights Legend Document Terminology PrefaceBIT Document Title Motorola Publication Number Related DocumentationPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv General Description IntroductionOte FeaturesMVME197LE Specifications SpecificationsCharacteristics Specifications Cooling Requirements FCC Compliance Equipment RequiredSupport Information Hardware Preparation Unpacking InstructionsHardware Preparation and Installation VMEbus Connector P1 Switch S1 Configuration SwitchesConfiguration Switch S1 General Information S1-1 to S1-8 OFF -- All Ones Factory Configuration Switch S6 Installation InstructionsConnectors MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Abort Switch S2 Controls and IndicatorsReset Switch S3 Memory Maps Front Panel Indicators DS1-DS6Processor Bus Memory Map Processor Bus Memory Map Local Devices Memory Map Address Range Devices Accessed Port SizeDetailed I/O Memory Maps 100 BusSwitch Register Memory Map108 110Memory Maps ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTER Ecdm CSR Register Memory MapDcam I2C Register Memory Map Dcam I2C Base Address = $C0 default OffsetOperating Instructions Offset VMEchip2 Memory Map Sheet 1Operating Instructions VMEchip2 Memory Map Sheet 2 Global Access BUS Watchdog Timeout Prescaler AdjustOperating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Gcsr Base Address = $FFF40100 VMEchip2 Memory Map Sheet 4Operating Instructions PCCchip2 Memory Map Printer SEL Interrupt Control Register $FFF42032 Printer Fault Interrupt Control Register $FFF42031Printer PE Interrupt Control Register $FFF42033 Printer Busy Interrupt Control Register $FFF42034Cirrus Logic CD2401 Serial Port Memory Map Cirrus Logic CD2400 Memory Map Offsets Size AccessBase Address Is $FFF45000 Data Bits Address D31 D16 D15 11 C710 Scsi Memory Map Accesses may be 8-bit or 32-bit, but not 16-bit12. MK48T08 BBRAM, TOD Clock Memory Map Address Range Description Size Bytes14. TOD Clock Memory Map 13. Bbram Configuration Area Memory MapData Bits Address Function 0460 BBRAM, TOD Clock Memory Map000000470476 VMEbus Memory Map VMEbus Accesses to the Local Peripheral Bus01-W3869B03A 5000Software Initialization Local Reset OperationMulti-MPU Programming Considerations User’s Manual Data Bus Structure MVME197LE Functional DescriptionMC88110 MPU Functional Description MC88110 Address Data MUX Address Bus Data Bus 256 BusSwitchMezzanine Address Bus Memory ArrayFlash Memory Battery Backup RAM and ClockOnboard Dram Interfaces VMEbus InterfaceSerial Port Interface Ethernet Interface Printer InterfacePeripheral Resources Programmable Tick TimersScsi Interface Scsi TerminationProcessor Bus Timeout Watchdog TimerLocal Peripheral Bus Timeout Interrupt SourcesMVME197LE/D2 Functional Description EIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Signal Name and Description Number MnemonicRing Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Numerics IndexIN-2 IN-3 Index

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