Motorola MVME197LE user manual Peripheral Resources, Scsi Interface, Scsi Termination

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MVME197LE Functional Description

the BBRAM, TOD Clock memory map description in the Operating Instructions chapter of this manual. The MVME197LE debugger has the capability to retrieve or set the Ethernet address.

If the data in the BBRAM is lost, the user should use the number on the VMEbus P2 connector label to restore it. Refer to the MVME197BUG 197Bug Debugging Package User’s Manual.

The Ethernet transceiver interface is located on the MVME197LE main module, and the industry standard connector is located on the MVME712X transition module.

Support functions for the 82596CA are provided by the PCCchip2. Refer to the 82596CA LAN Coprocessor User’s Manual and to the PCCchip2 chapter in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for detailed programming information.

SCSI Interface

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The MVME197LE provides for mass storage subsystems through the industry- standard SCSI bus. These subsystems may include hard and floppy disk drives, streaming tape drives, and other mass storage devices. The SCSI interface is implemented using the NCR 53C710 SCSI I/O controller.

Support functions for the 53C710 are provided by the PCCchip2. Refer to the NCR 53C710 SCSI I/O Processor Data Manual and to the PCCchip2 chapter in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for detailed programming information.

SCSI Termination

The system configurer must ensure that the SCSI bus is terminated properly. On the MVME197LE, the terminators are located on the P2 transition board. The +5V power to the SCSI bus termination resistors is provided by the P2 transition board.

Peripheral Resources

The MVME197LE includes many resources for the local processor. These include tick timers, software programmable hardware interrupts, watchdog timer, and local peripheral bus timeout.

Programmable Tick Timers

Six 32-bit programmable tick timers with 1 μsec resolution are provided, two in the BusSwitch, two in the VMEchip2, and two in the PCCchip2. The tick timers can be programmed to generate periodic interrupts to the processor.

MVME197LE/D2

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Contents MVME197LE/D2 MVME197LERestricted Rights Legend Document Terminology PrefaceBIT Document Title Motorola Publication Number Related DocumentationPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv General Description IntroductionOte FeaturesCharacteristics Specifications SpecificationsMVME197LE Specifications Cooling Requirements FCC Compliance Equipment RequiredSupport Information Hardware Preparation Unpacking InstructionsHardware Preparation and Installation VMEbus Connector P1 Configuration Switch S1 General Information Configuration SwitchesSwitch S1 S1-1 to S1-8 OFF -- All Ones Factory Configuration Connectors Installation InstructionsSwitch S6 MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Reset Switch S3 Controls and IndicatorsAbort Switch S2 Processor Bus Memory Map Front Panel Indicators DS1-DS6Memory Maps Processor Bus Memory Map Local Devices Memory Map Address Range Devices Accessed Port SizeDetailed I/O Memory Maps 100 BusSwitch Register Memory Map108 110Memory Maps ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTER Ecdm CSR Register Memory MapDcam I2C Register Memory Map Dcam I2C Base Address = $C0 default OffsetOperating Instructions Offset VMEchip2 Memory Map Sheet 1Operating Instructions VMEchip2 Memory Map Sheet 2 Global Access BUS Watchdog Timeout Prescaler AdjustOperating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Gcsr Base Address = $FFF40100 VMEchip2 Memory Map Sheet 4Operating Instructions PCCchip2 Memory Map Printer SEL Interrupt Control Register $FFF42032 Printer Fault Interrupt Control Register $FFF42031Printer PE Interrupt Control Register $FFF42033 Printer Busy Interrupt Control Register $FFF42034Base Address Is $FFF45000 Cirrus Logic CD2400 Memory Map Offsets Size AccessCirrus Logic CD2401 Serial Port Memory Map Data Bits Address D31 D16 D15 11 C710 Scsi Memory Map Accesses may be 8-bit or 32-bit, but not 16-bit12. MK48T08 BBRAM, TOD Clock Memory Map Address Range Description Size BytesData Bits Address Function 13. Bbram Configuration Area Memory Map14. TOD Clock Memory Map 000000470476 BBRAM, TOD Clock Memory Map0460 VMEbus Memory Map VMEbus Accesses to the Local Peripheral Bus01-W3869B03A 5000Multi-MPU Programming Considerations Local Reset OperationSoftware Initialization User’s Manual MC88110 MPU MVME197LE Functional DescriptionData Bus Structure Functional Description MC88110 Address Data MUX Address Bus Data Bus 256 BusSwitchMezzanine Address Bus Memory ArrayOnboard Dram Battery Backup RAM and ClockFlash Memory Serial Port Interface VMEbus InterfaceInterfaces Ethernet Interface Printer InterfacePeripheral Resources Programmable Tick TimersScsi Interface Scsi TerminationProcessor Bus Timeout Watchdog TimerLocal Peripheral Bus Timeout Interrupt SourcesMVME197LE/D2 Functional Description EIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Signal Name and Description Number MnemonicRing Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Numerics IndexIN-2 IN-3 Index

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