Motorola MVME197LE user manual PCCchip2 Memory Map

Page 49

MVME197LE/D2

3-19

Table 3-7. PCCchip2 Memory Map

PCCchip2 LCSR Base Address = $FFF42000

OFFSET:

 

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

 

D18

 

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

 

D6

D5

D4

D3

 

D2

D1

 

D0

00

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPU

MSTR

FAST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CHIP ID

 

 

 

 

 

 

CHIP REVISION

 

 

 

 

DR0

 

 

 

 

040

INT

BRAM

 

 

 

 

VECTOR BASE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EN

 

 

 

 

 

 

 

 

 

 

 

 

04

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TIC TIMER 1 COMPARE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

08

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TIC TIMER 1 COUNTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TIC TIMER 2 COMPARE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TIC TIMER 2 COUNTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OVERFLOW

 

 

CLR

COUN

COUN

 

 

OVERFLOW

 

 

 

CLR

COUN

COUN

 

 

PRESCALER COUNT

 

 

 

 

PRESCALER CLOCK ADJUST

 

 

 

COUNTER 2

 

 

OVF

EN

EN

 

 

COUNTER 1

 

 

 

OVF

EN

 

EN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

2

2

 

 

 

 

 

 

 

1

1

 

1

18

GPI

GPI

GPI

GPI

GPI

 

GPI

 

 

 

 

 

 

 

 

 

 

 

 

 

TIC2

TIC2

TIC2

TIC TIMER 2

 

 

 

TIC1

TIC1

TIC1

 

TIC TIMER 1

PLTY

E/L*

INT

IEN

ICLR

IRQ LEVEL

 

 

 

 

 

 

GPI

 

GIOE

GPO

 

 

INT

IEN

ICLR

IRQ LEVEL

 

 

 

INT

IEN

ICLR

 

IRQ LEVEL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1C

 

 

 

SCC

SCC

SCC

SCC

SCC

 

 

SCC

SCC

SCC

 

SCC MODEM

 

 

SCC

SCC

SCC

SCC TRANSMIT

SCC

 

SCC

SCC

SCC

SCC

 

SCC RECEIVE

 

 

 

RTRY

PAR

EXT

LTO

SCLR

 

 

MDM

MDM

MDM

 

IRQ LEVEL

 

 

TX

TX

TX

IRQ LEVEL

SC1

 

SC2

IRQ

IEN

AVEC

 

IRQ LEVEL

 

 

 

 

ERR

ERR

ERR

ERR

 

 

 

 

 

 

 

 

 

 

 

 

 

IRQ

IEN

AVEC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCC MODEM PIACK

 

 

 

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCC TRANSMIT PIACK

 

 

 

 

 

 

 

 

 

 

 

 

 

SCC RECEIVE PIACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

 

 

 

 

LAN

LAN

LAN

LAN

 

 

 

 

 

 

 

 

 

 

LAN

LAN

LAN

LAN

LAN

 

LAN

 

LAN

 

LAN

LAN

LAN

LAN

 

 

LAN ERR

 

 

 

 

 

PAR

EXT

LTO

SCLR

 

 

 

 

 

 

 

 

 

 

PLTY

E/L*

INT

IEN

ICLR

IRQ LEVEL

SC1

 

SC2

ERR

ERR

ERR

 

IRQ LEVEL

 

 

 

 

 

ERR

ERR

ERR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT

IEN

ICLR

 

 

 

 

 

2C

 

 

 

 

SCSI

SCSI

SCSI

SCSI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCSI

SCSI

 

 

 

SCSI INT

 

 

 

 

 

PAR

EXT

LTO

SCLR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IRQ

IEN

 

 

IRQ LEVEL

 

 

 

 

 

ERR

ERR

ERR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30

PRTR

PRTR

PRTR

PRTR

PRTR

PRTR ACK

PRTR

PRTR

PRTR

PRTR

PRTR

 

PRTR FAULT

PRTR

PRTR

PRTR

PRTR

PRTR

PRTR SEL

PRTR

PRTR

PRTR

PRTR

PRTR

 

 

PRTR PE

 

ACK

ACK

ACK

ACK

ACK

IRQ LEVEL

FLT

FLT

FLT

FLT

FLT

 

IRQ LEVEL

SEL

SEL

SEL

SEL

SEL

IRQ LEVEL

PE

 

PE

PE

PE

PE

 

IRQ LEVEL

 

PLTY

E/L*

INT

IEN

ICLR

 

 

 

PLTY

E/L*

INT

IEN

ICLR

 

 

 

 

 

PLTY

E/L*

INT

IEN

ICLR

 

 

 

PLTY

 

E/L*

INT

IEN

ICLR

 

 

 

 

 

34

PRTR

PRTR

PRTR

PRTR

PRTR

PRTR BSY

 

 

 

 

 

 

 

 

 

 

PRTR

 

 

PRTR

PRTR

PRTR

PRTR

PRTR

 

 

 

 

PRTR

PRTR

PRTR

PRTR

PRTR

BSY

BSY

BSY

BSY

BSY

IRQ LEVEL

 

 

 

 

 

 

 

 

 

 

ANY

 

 

ACK

FLT

SEL

PE

BSY

 

 

 

 

DAT

INP

 

STB

FAST

 

MAN

 

PLTY

E/L*

INT

IEN

ICLR

 

 

 

 

 

 

 

 

 

 

 

 

 

INT

 

 

 

 

 

 

 

 

 

 

 

ENBL

 

 

 

ASTB

 

STB

38

 

 

 

 

 

 

 

CHIP SPEED

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PRINTER DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTERRUPT

 

 

 

 

 

 

 

INTERRUPT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IPL LEVEL

 

 

 

 

 

 

 

MASK LEVEL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

 

D18

 

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

 

D6

D5

D4

D3

 

D2

D1

 

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Maps

3

Page 48 Page 50
Image 49
Page 48 Page 50
Contents MVME197LE/D2 MVME197LERestricted Rights Legend Document Terminology PrefaceBIT Document Title Motorola Publication Number Related DocumentationPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv General Description IntroductionOte FeaturesMVME197LE Specifications SpecificationsCharacteristics Specifications Cooling Requirements FCC Compliance Equipment RequiredSupport Information Hardware Preparation Unpacking InstructionsHardware Preparation and Installation VMEbus Connector P1 Switch S1 Configuration SwitchesConfiguration Switch S1 General Information S1-1 to S1-8 OFF -- All Ones Factory Configuration Switch S6 Installation InstructionsConnectors MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Abort Switch S2 Controls and IndicatorsReset Switch S3 Memory Maps Front Panel Indicators DS1-DS6Processor Bus Memory Map Processor Bus Memory Map Local Devices Memory Map Address Range Devices Accessed Port SizeDetailed I/O Memory Maps 100 BusSwitch Register Memory Map108 110Memory Maps ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTER Ecdm CSR Register Memory MapDcam I2C Register Memory Map Dcam I2C Base Address = $C0 default OffsetOperating Instructions Offset VMEchip2 Memory Map Sheet 1Operating Instructions VMEchip2 Memory Map Sheet 2 Global Access BUS Watchdog Timeout Prescaler AdjustOperating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Gcsr Base Address = $FFF40100 VMEchip2 Memory Map Sheet 4Operating Instructions PCCchip2 Memory Map Printer SEL Interrupt Control Register $FFF42032 Printer Fault Interrupt Control Register $FFF42031Printer PE Interrupt Control Register $FFF42033 Printer Busy Interrupt Control Register $FFF42034Cirrus Logic CD2401 Serial Port Memory Map Cirrus Logic CD2400 Memory Map Offsets Size AccessBase Address Is $FFF45000 Data Bits Address D31 D16 D15 11 C710 Scsi Memory Map Accesses may be 8-bit or 32-bit, but not 16-bit12. MK48T08 BBRAM, TOD Clock Memory Map Address Range Description Size Bytes14. TOD Clock Memory Map 13. Bbram Configuration Area Memory MapData Bits Address Function 0460 BBRAM, TOD Clock Memory Map000000470476 VMEbus Memory Map VMEbus Accesses to the Local Peripheral Bus01-W3869B03A 5000Software Initialization Local Reset OperationMulti-MPU Programming Considerations User’s Manual Data Bus Structure MVME197LE Functional DescriptionMC88110 MPU Functional Description MC88110 Address Data MUX Address Bus Data Bus 256 BusSwitchMezzanine Address Bus Memory ArrayFlash Memory Battery Backup RAM and ClockOnboard Dram Interfaces VMEbus InterfaceSerial Port Interface Ethernet Interface Printer InterfacePeripheral Resources Programmable Tick TimersScsi Interface Scsi TerminationProcessor Bus Timeout Watchdog TimerLocal Peripheral Bus Timeout Interrupt SourcesMVME197LE/D2 Functional Description EIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Signal Name and Description Number MnemonicRing Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Numerics IndexIN-2 IN-3 Index
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