Motorola MVME197LE user manual Processor Bus Memory Map

Page 33

Memory Maps

The memory maps of MVME197LE devices are provided in the following tables. Table 3-1 is the entire map from $00000000 to $FFFFFFFF. Many areas of the map are user-programmable, and suggested uses are shown in the table. This is assuming no address translation is used between the processor and local peripheral bus and between the local peripheral bus and VMEbus. The cache inhibit function is programmable in the MC88110. The onboard I/O space must be marked cache inhibit and serialized in its page table. Table 3-2 further defines the map for the local devices.

3

Table 3-1. Processor Bus Memory Map

	Address	Devices	Port		Software
	Address	Devices	Port	Size	Cache	Notes
	Range	Accessed	Size	Size	Cache	Notes
	Range	Accessed	Size		Inhibit
					Inhibit


	$00000000 - (DRAMSIZE -1)	User Programmable	D64	DRAMSIZE	N	1
		(Onboard DRAM)

	DRAMSIZE - $FF7FFFFF	User Programmable	D32/D16	3GB	?	2,3
		(VMEbus)

	$FF800000 - $FFBFFFFF	Flash Memory	D32	4MB	N	5

	$FFC00000 - $FFEFFFFF	reserved	---	3MB	---	4

	$FFF00000 - $FFFEFFFF	Local Devices	D32-D8	1MB	Y	---
		(Refer to next table)

	$FFFF0000 - $FFFFFFFF	User Programmable	D32/D16	64KB	?	1,3
		(VMEbus A16)

Notes

1.This area is user-programmable. The suggested use is

shown in the table. The DRAM decoder is programmed in the DCAM through the ECDM I2CBus interface. The Processor Bus to Local Peripheral Bus and the Local Peripheral Bus to Processor Bus decoders are programmed in the BusSwitch. The Local Peripheral to VMEbus (master) and VMEbus to Local Peripheral Bus (slave) decoders are programmed in the VMEchip2.

2.Size is approximate.

3.Cache inhibit depends on devices in area mapped.

4.This area is not decoded. If these locations are accessed and the local peripheral bus timer is enabled, the cycle times out and is terminated by a TEA signal.

5.This area is user programmable via the BusSwitch. Default size is 4 megabytes.

MVME197LE/D2

3-3

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Contents MVME197LE/D2 MVME197LERestricted Rights Legend Document Terminology PrefaceBIT Document Title Motorola Publication Number Related DocumentationPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv General Description IntroductionOte FeaturesSpecifications MVME197LE SpecificationsCharacteristics Specifications Cooling Requirements FCC Compliance Equipment RequiredSupport Information Hardware Preparation Unpacking InstructionsHardware Preparation and Installation VMEbus Connector P1 Configuration Switches Switch S1Configuration Switch S1 General Information S1-1 to S1-8 OFF -- All Ones Factory Configuration Installation Instructions Switch S6Connectors MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Controls and Indicators Abort Switch S2Reset Switch S3 Front Panel Indicators DS1-DS6 Memory MapsProcessor Bus Memory Map Processor Bus Memory Map Local Devices Memory Map Address Range Devices Accessed Port SizeDetailed I/O Memory Maps 100 BusSwitch Register Memory Map108 110Memory Maps ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTER Ecdm CSR Register Memory MapDcam I2C Register Memory Map Dcam I2C Base Address = $C0 default OffsetOperating Instructions Offset VMEchip2 Memory Map Sheet 1Operating Instructions VMEchip2 Memory Map Sheet 2 Global Access BUS Watchdog Timeout Prescaler AdjustOperating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Gcsr Base Address = $FFF40100 VMEchip2 Memory Map Sheet 4Operating Instructions PCCchip2 Memory Map Printer SEL Interrupt Control Register $FFF42032 Printer Fault Interrupt Control Register $FFF42031Printer PE Interrupt Control Register $FFF42033 Printer Busy Interrupt Control Register $FFF42034Cirrus Logic CD2400 Memory Map Offsets Size Access Cirrus Logic CD2401 Serial Port Memory MapBase Address Is $FFF45000 Data Bits Address D31 D16 D15 11 C710 Scsi Memory Map Accesses may be 8-bit or 32-bit, but not 16-bit12. MK48T08 BBRAM, TOD Clock Memory Map Address Range Description Size Bytes13. Bbram Configuration Area Memory Map 14. TOD Clock Memory MapData Bits Address Function BBRAM, TOD Clock Memory Map 0460000000470476 VMEbus Memory Map VMEbus Accesses to the Local Peripheral Bus01-W3869B03A 5000Local Reset Operation Software InitializationMulti-MPU Programming Considerations User’s Manual MVME197LE Functional Description Data Bus StructureMC88110 MPU Functional Description MC88110 Address Data MUX Address Bus Data Bus 256 BusSwitchMezzanine Address Bus Memory ArrayBattery Backup RAM and Clock Flash MemoryOnboard Dram VMEbus Interface InterfacesSerial Port Interface Ethernet Interface Printer InterfacePeripheral Resources Programmable Tick TimersScsi Interface Scsi TerminationProcessor Bus Timeout Watchdog TimerLocal Peripheral Bus Timeout Interrupt SourcesMVME197LE/D2 Functional Description EIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Signal Name and Description Number MnemonicRing Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Numerics IndexIN-2 IN-3 Index

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