Motorola MVME197LE user manual Controls and Indicators, Abort Switch S2, Reset Switch S3

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OPERATING INSTRUCTIONS

3

Introduction

This chapter provides the necessary information to use the MVME197LE VMEmodule in a system configuration. This includes controls and indicators, memory maps, and software initialization of the module.

Controls and Indicators

The MVME197LE Single Board Computer has two push-botton switches (ABORT and RESET) and six LED indicators (FAIL, SCON, RUN, LAN, VME, and SCSI), all located on the front panel of the module.

ABORT Switch S2

When enabled by software, the front panel ABORT switch (S2) generates an NMI (Non-Maskable Interrupt) type interrupt at a user-programmable level. It is normally used to abort program execution and return to the 197Bug debugger. Refer to the VMEchip2 chapter of the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for more information.

RESET Switch S3

The RESET switch (S3) will reset all the onboard devices and drive the SYSRESET* signal if the MVME197LE module is the system controller. The RESET switch (S3) will reset all the onboard devices, with the exception of the DCAM and ECDM, if the MVME197LE module is not the system controller. The VMEchip2 generates the SYSREST* signal. The BusSwitch combines the local reset and the reset switch to generate a local board reset. Refer to the Reset Driver section in the VMEchip2 chapter of the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for more information.

The BusSwitch receives the reset switch signal, debounces it and combines with the reset signal from the VMEchip2 to generate a board reset signal.

The VMEchip2 includes both a global and a local reset driver. When the chip operates as the VMEbus system controller, the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET*. A SYSRESET* may be generated by the RESET switch, a power up reset, a watchdog timeout, or

MVME197LE/D23-1

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Contents MVME197LE/D2 MVME197LERestricted Rights Legend Document Terminology PrefaceBIT Document Title Motorola Publication Number Related DocumentationPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv General Description IntroductionOte FeaturesMVME197LE Specifications SpecificationsCharacteristics Specifications Cooling Requirements FCC Compliance Equipment RequiredSupport Information Hardware Preparation Unpacking InstructionsHardware Preparation and Installation VMEbus Connector P1 Switch S1 Configuration SwitchesConfiguration Switch S1 General Information S1-1 to S1-8 OFF -- All Ones Factory Configuration Switch S6 Installation InstructionsConnectors MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Abort Switch S2 Controls and IndicatorsReset Switch S3 Memory Maps Front Panel Indicators DS1-DS6Processor Bus Memory Map Processor Bus Memory Map Local Devices Memory Map Address Range Devices Accessed Port SizeDetailed I/O Memory Maps 110 BusSwitch Register Memory Map100 108Memory Maps ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTER Ecdm CSR Register Memory MapDcam I2C Register Memory Map Dcam I2C Base Address = $C0 default OffsetOperating Instructions Offset VMEchip2 Memory Map Sheet 1Operating Instructions VMEchip2 Memory Map Sheet 2 Global Access BUS Watchdog Timeout Prescaler AdjustOperating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Gcsr Base Address = $FFF40100 VMEchip2 Memory Map Sheet 4Operating Instructions PCCchip2 Memory Map Printer Busy Interrupt Control Register $FFF42034 Printer Fault Interrupt Control Register $FFF42031Printer SEL Interrupt Control Register $FFF42032 Printer PE Interrupt Control Register $FFF42033Cirrus Logic CD2401 Serial Port Memory Map Cirrus Logic CD2400 Memory Map Offsets Size AccessBase Address Is $FFF45000 Data Bits Address D31 D16 D15 Address Range Description Size Bytes Accesses may be 8-bit or 32-bit, but not 16-bit11 C710 Scsi Memory Map 12. MK48T08 BBRAM, TOD Clock Memory Map14. TOD Clock Memory Map 13. Bbram Configuration Area Memory MapData Bits Address Function 0460 BBRAM, TOD Clock Memory Map000000470476 5000 VMEbus Accesses to the Local Peripheral BusVMEbus Memory Map 01-W3869B03ASoftware Initialization Local Reset OperationMulti-MPU Programming Considerations User’s Manual Data Bus Structure MVME197LE Functional DescriptionMC88110 MPU Functional Description Memory Array Bus Data Bus 256 BusSwitchMC88110 Address Data MUX Address Mezzanine Address BusFlash Memory Battery Backup RAM and ClockOnboard Dram Interfaces VMEbus InterfaceSerial Port Interface Ethernet Interface Printer InterfaceScsi Termination Programmable Tick TimersPeripheral Resources Scsi InterfaceInterrupt Sources Watchdog TimerProcessor Bus Timeout Local Peripheral Bus TimeoutMVME197LE/D2 Functional Description EIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Signal Name and Description Number MnemonicRing Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Numerics IndexIN-2 IN-3 Index

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