Motorola MVME197LE user manual VMEchip2 Memory Map Sheet 3

Page 45

MVME197LE/D2

3-15

Table 3-6. VMEchip2 Memory Map (Continued)

(Sheet 3 of 4)

VMEchip2 LCSR Base Address = $FFF40000

OFFSET:

 

D31

D30

D29

 

D28

D27

D26

D25

 

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

 

D4

D3

D2

D1

 

D0

68

AC

AB

SYS

 

MWP

PE

IRQ1

TIC

 

TIC

VME

DMAC

GCSR

GCSR

GCSR

GCSR

GCSR

GCSR

LB

LB

LB

LB

LB

LB

LB

LB

SPARE

VME

VME

 

VME

VME

VME

VME

 

VME

FAIL

SW

FAIL

 

ERR

IRQ

EDGE

TIM2

 

TIM1

IACK

IRQ

SIG3

SIG2

SIG1

SIG0

LM1

LM0

SW7

SW6

SW5

SW4

SW3

SW2

SW1

SW0

 

IRQ7

IRQ6

 

IRQ5

IRQ4

IRQ3

IRQ2

 

IRQ1

 

IRQ

IRQ

IRQ

 

IRQ

 

IRQ

IRQ

 

IRQ

IRQ

 

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

 

IRQ

IRQ

 

IRQ

IRQ

IRQ

IRQ

 

IRQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6C

EN

EN

EN

 

EN

EN

EN

EN

 

EN

EN

EN

EN

EN

EN

EN

EN

EN

EN

EN

EN

EN

EN

EN

EN

EN

EN

EN

EN

 

EN

EN

EN

EN

 

EN

IRQ

IRQ

IRQ

 

IRQ

IRQ

IRQ

IRQ

 

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

 

IRQ

IRQ

IRQ

IRQ

 

IRQ

 

31

30

29

 

28

27

26

25

 

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

 

4

3

2

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

70

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SET

SET

SET

SET

SET

SET

SET

SET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

 

 

 

 

 

 

 

 

 

 

74

CLR

CLR

CLR

 

CLR

CLR

CLR

CLR

 

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

 

 

 

 

 

 

 

 

 

 

IRQ

IRQ

IRQ

 

IRQ

IRQ

IRQ

IRQ

 

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

 

 

 

 

 

 

 

 

 

 

 

31

30

29

 

28

27

26

25

 

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

 

 

 

 

 

 

 

 

 

 

78

 

 

ACFAIL

 

 

 

ABORT

 

 

 

SYSFAIL

 

MASTER WRITE

 

PARITY ERROR

 

 

IRQ1

 

 

TICK TIMER 2

 

TICK TIMER 1

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

POST ERROR

 

IRQ LEVEL

 

EDGE-SENSITIVE

 

IRQ LEVEL

 

IRQ LEVEL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IRQ LEVEL

 

 

 

 

 

IRQ LEVEL

 

 

 

 

 

 

 

 

 

 

7C

 

 

VMEbus

 

 

 

DMAC

 

 

 

GCSR

 

 

 

GCSR

 

 

 

GCSR

 

 

 

GCSR

 

 

 

GCSR

 

 

 

GCSR

 

 

ACKNOWLEDGE

 

IRQ LEVEL

 

 

SIG 3

 

 

 

SIG 2

 

 

 

SIG 1

 

 

 

SIG 0

 

 

 

LM 1

 

 

 

LM 0

 

 

 

IRQ LEVEL

 

 

 

 

 

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

80

 

 

SW7

 

 

 

SW6

 

 

 

SW5

 

 

 

SW4

 

 

 

SW3

 

 

 

SW2

 

 

 

SW1

 

 

 

SW0

 

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

84

 

 

SPARE

 

 

 

VMEbus

 

 

 

VMEbus

 

 

 

VMEbus

 

 

 

VMEbus

 

 

 

VMEbus

 

 

 

VMEbus

 

 

 

VMEbus

 

 

IRQ LEVEL

 

 

IRQ7

 

 

 

IRQ6

 

 

 

IRQ5

 

 

 

IRQ4

 

 

 

IRQ3

 

 

 

IRQ2

 

 

 

IRQ1

 

 

 

 

 

 

 

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

 

IRQ LEVEL

88

 

VECTOR BASE

 

 

VECTOR BASE

 

MST

SYS

AC

ABORT

 

GENERAL

 

 

GENERAL

 

 

GENERAL

 

 

 

 

 

 

 

 

 

 

 

 

REGISTER 0

 

 

REGISTER 1

 

IRQ

FAIL

FAIL

LEVEL

 

PURPOSE

 

 

PURPOSE

 

 

PURPOSE

 

 

 

GENERAL PURPOSE INPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EN

LEVEL

LEVEL

 

 

I/O ENABLE

 

 

I/O OUTPUT

 

 

I/O INPUT

 

 

 

 

 

 

 

 

 

 

 

 

D31

D30

D29

 

D28

D27

D26

D25

 

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

 

D4

D3

D2

D1

 

D0

 

LB

= Local Bus

 

 

 

 

 

 

 

 

 

 

 

 

 

VB

= VMEbus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(LB)

= Local Bus Slave

 

 

 

 

 

 

 

 

 

 

 

(VB)

= VMEbus Slave

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LV

= Local Bus to VMEbus

 

 

 

 

 

 

 

 

 

(XX)

= Not Used on the MVME197 Series

 

 

 

 

 

 

 

 

 

Memory Maps

3

Image 45
Contents MVME197LE/D2 MVME197LERestricted Rights Legend Document Terminology PrefaceBIT Document Title Motorola Publication Number Related DocumentationPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv General Description IntroductionOte FeaturesSpecifications MVME197LE SpecificationsCharacteristics Specifications Cooling Requirements FCC Compliance Equipment RequiredSupport Information Hardware Preparation Unpacking InstructionsHardware Preparation and Installation VMEbus Connector P1 Configuration Switches Switch S1Configuration Switch S1 General Information S1-1 to S1-8 OFF -- All Ones Factory Configuration Installation Instructions Switch S6Connectors MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Controls and Indicators Abort Switch S2Reset Switch S3 Front Panel Indicators DS1-DS6 Memory MapsProcessor Bus Memory Map Processor Bus Memory Map Local Devices Memory Map Address Range Devices Accessed Port SizeDetailed I/O Memory Maps 100 BusSwitch Register Memory Map108 110Memory Maps ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTER Ecdm CSR Register Memory MapDcam I2C Register Memory Map Dcam I2C Base Address = $C0 default OffsetOperating Instructions Offset VMEchip2 Memory Map Sheet 1Operating Instructions VMEchip2 Memory Map Sheet 2 Global Access BUS Watchdog Timeout Prescaler AdjustOperating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Gcsr Base Address = $FFF40100 VMEchip2 Memory Map Sheet 4Operating Instructions PCCchip2 Memory Map Printer SEL Interrupt Control Register $FFF42032 Printer Fault Interrupt Control Register $FFF42031Printer PE Interrupt Control Register $FFF42033 Printer Busy Interrupt Control Register $FFF42034Cirrus Logic CD2400 Memory Map Offsets Size Access Cirrus Logic CD2401 Serial Port Memory MapBase Address Is $FFF45000 Data Bits Address D31 D16 D15 11 C710 Scsi Memory Map Accesses may be 8-bit or 32-bit, but not 16-bit12. MK48T08 BBRAM, TOD Clock Memory Map Address Range Description Size Bytes13. Bbram Configuration Area Memory Map 14. TOD Clock Memory MapData Bits Address Function BBRAM, TOD Clock Memory Map 0460000000470476 VMEbus Memory Map VMEbus Accesses to the Local Peripheral Bus01-W3869B03A 5000Local Reset Operation Software InitializationMulti-MPU Programming Considerations User’s Manual MVME197LE Functional Description Data Bus StructureMC88110 MPU Functional Description MC88110 Address Data MUX Address Bus Data Bus 256 BusSwitchMezzanine Address Bus Memory ArrayBattery Backup RAM and Clock Flash MemoryOnboard Dram VMEbus Interface InterfacesSerial Port Interface Ethernet Interface Printer InterfacePeripheral Resources Programmable Tick TimersScsi Interface Scsi TerminationProcessor Bus Timeout Watchdog TimerLocal Peripheral Bus Timeout Interrupt SourcesMVME197LE/D2 Functional Description EIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Signal Name and Description Number MnemonicRing Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Numerics IndexIN-2 IN-3 Index
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