Motorola MVME197LE user manual VMEchip2 Memory Map Sheet 1, Offset

Page 41

MVME197LE/D2

3-11

Table 3-6. VMEchip2 Memory Map

(Sheet 1 of 4)

VMEchip2 LCSR Base Address = $FFF40000

OFFSET:

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

00

VMEbus SLAVE ENDING ADDRESS 1

VMEbus SLAVE STARTING ADDRESS 1

04

VMEbus SLAVE ENDING ADDRESS 2

VMEbus SLAVE STARTING ADDRESS 2

08

VMEbus SLAVE ADDRESS TRANSLATION ADDRESS 1

VMEbus SLAVE ADDRESS TRANSLATION SELECT 1

0C

VMEbus SLAVE ADDRESS TRANSLATION ADDRESS 2

VMEbus SLAVE ADDRESS TRANSLATION SELECT 2

10

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

SNP

WP

SUP

USR

A32

A24

D64

BLK

PGM

DAT

SNP

WP

SUP

USR

A32

A24

D64

BLK

PGM

DAT

2

2

2

2

2

2

2

2

2

2

1

1

1

1

1

1

1

1

1

1

14

LOCAL BUS SLAVE ENDING ADDRESS 1

LOCAL BUS SLAVE STARTING ADDRESS 1

18

LOCAL BUS SLAVE ENDING ADDRESS 2

LOCAL BUS SLAVE STARTING ADDRESS 2

1C

LOCAL BUS SLAVE ENDING ADDRESS 3

LOCAL BUS SLAVE STARTING ADDRESS 3

20

LOCAL BUS SLAVE ENDING ADDRESS 4

LOCAL BUS SLAVE STARTING ADDRESS 4

24

LOCAL BUS SLAVE ADDRESS TRANSLATION ADDRESS 4

LOCAL BUS SLAVE ADDRESS TRANSLATION SELECT 4

28

(LB)

(LB)

(LB)

(LB)

(LB)

(LB)

(LB)

(LB)

D16

WP

(LB) AM 4

D16

WP

(LB) AM 3

D16

WP

(LB) AM 2

D16

WP

(LB) AM 1

EN

EN

EN

EN

EN

EN

EN

EN

2C

(VB) GCSR

LB

LB

LB

LB

LB

LB

LB

LB

LB

LB

LB

LB

ROM

ROM BANK B

ROM BANK A

(VB) GCSR GROUP ADDRESS

BOARD

EN4

EN3

EN2

EN1

I2

I2

I2

I2

I1

I1

I1

I1

SIZE

SPEED

SPEED

ADDRESS

EN

WP

SU

PD

EN

D16

WP

SU

(XX)

(XX)

(XX)

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

LB

= Local Bus

VB

= VMEbus

(LB)

= Local Bus Slave

(VB)

= VMEbus Slave

LV

= Local Bus to VMEbus

(XX) = Not Used on the MVME197 Series

Memory Maps

3

Image 41

Contents MVME197LE/D2 MVME197LERestricted Rights Legend Document Terminology PrefaceBIT Document Title Motorola Publication Number Related DocumentationPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv General Description IntroductionOte FeaturesCharacteristics Specifications SpecificationsMVME197LE Specifications Cooling Requirements FCC Compliance Equipment RequiredSupport Information Hardware Preparation Unpacking InstructionsHardware Preparation and Installation VMEbus Connector P1 Configuration Switch S1 General Information Configuration SwitchesSwitch S1 S1-1 to S1-8 OFF -- All Ones Factory Configuration Connectors Installation InstructionsSwitch S6 MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Reset Switch S3 Controls and IndicatorsAbort Switch S2 Processor Bus Memory Map Front Panel Indicators DS1-DS6Memory Maps Processor Bus Memory Map Local Devices Memory Map Address Range Devices Accessed Port SizeDetailed I/O Memory Maps 100 BusSwitch Register Memory Map108 110Memory Maps ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTER Ecdm CSR Register Memory MapDcam I2C Register Memory Map Dcam I2C Base Address = $C0 default OffsetOperating Instructions Offset VMEchip2 Memory Map Sheet 1Operating Instructions VMEchip2 Memory Map Sheet 2 Global Access BUS Watchdog Timeout Prescaler AdjustOperating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Gcsr Base Address = $FFF40100 VMEchip2 Memory Map Sheet 4Operating Instructions PCCchip2 Memory Map Printer SEL Interrupt Control Register $FFF42032 Printer Fault Interrupt Control Register $FFF42031Printer PE Interrupt Control Register $FFF42033 Printer Busy Interrupt Control Register $FFF42034Base Address Is $FFF45000 Cirrus Logic CD2400 Memory Map Offsets Size AccessCirrus Logic CD2401 Serial Port Memory Map Data Bits Address D31 D16 D15 11 C710 Scsi Memory Map Accesses may be 8-bit or 32-bit, but not 16-bit12. MK48T08 BBRAM, TOD Clock Memory Map Address Range Description Size BytesData Bits Address Function 13. Bbram Configuration Area Memory Map14. TOD Clock Memory Map 000000470476 BBRAM, TOD Clock Memory Map0460 VMEbus Memory Map VMEbus Accesses to the Local Peripheral Bus01-W3869B03A 5000Multi-MPU Programming Considerations Local Reset OperationSoftware Initialization User’s Manual MC88110 MPU MVME197LE Functional DescriptionData Bus Structure Functional Description MC88110 Address Data MUX Address Bus Data Bus 256 BusSwitchMezzanine Address Bus Memory ArrayOnboard Dram Battery Backup RAM and ClockFlash Memory Serial Port Interface VMEbus InterfaceInterfaces Ethernet Interface Printer InterfacePeripheral Resources Programmable Tick TimersScsi Interface Scsi TerminationProcessor Bus Timeout Watchdog TimerLocal Peripheral Bus Timeout Interrupt SourcesMVME197LE/D2 Functional Description EIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Signal Name and Description Number MnemonicRing Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Numerics IndexIN-2 IN-3 Index

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