Motorola MVME197LE user manual Cooling Requirements

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1		General Information
1		Table 1-1. MVME197LE Specifications (Continued)



		Characteristics	Specifications


		Physical dimensions:	Double-high VMEboard
		PC board
		Height	9.187 inches (233.35 mm)
		Width	6.299 inches (160.00 mm)
		Thickness	0.063 inch (1.60 mm)
		PC board with connectors
		and front panel
		Height	10.309 inches (261.85 mm)
		Width	7.4 inches (188.00 mm)
		Thickness	0.80 inch (20.32 mm)
		Board connectors:
		P1 connector	A 96-pin connector which provides the interface to the
			VMEbus signals.
		P2 connector	A 96-pin connector which provides the interface to the
			extended VMEbus signals and other I/O signals.
		J1 connector	A 20-pin connector which provides the interface to the
			remote reset, abort, the LEDs, and three general purpose I/O
			signals.
		J2 connector	A 249-pin connector which provides the interface to the
			MC88110 address, data, and control signals to and from the
			mezzanine expansion.

Cooling Requirements

The Motorola MVME197LE VMEmodule is specified, designed, and tested to operate reliably with an incoming air temperature range from 0° to 55° C (32° to 131° F) with forced air cooling at a velocity typically achievable by using a 100 CFM axial fan. Temperature qualification is performed in a standard Motorola VMEsystem 3000 chassis. Twenty-five watt load boards are inserted in two card slots, one on each side, adjacent to the board under test, to simulate a high power density system configuration. An assembly of three axial fans, rated at 100 CFM per fan, is placed directly under the VME card cage. The incoming air temperature is measured between the fan assembly and the card cage, where the incoming airstream first encounters the module under test. Test software is executed as the module is subjected to ambient temperature variations. Case temperatures of critical, high power density integrated circuits are monitored to ensure component vendors specifications are not exceeded.

1-4	User’s Manual

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Contents MVME197LE MVME197LE/D2Restricted Rights Legend Preface Document TerminologyBIT Related Documentation Document Title Motorola Publication NumberPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv Introduction General DescriptionFeatures OteSpecifications MVME197LE SpecificationsCharacteristics Specifications Cooling Requirements Equipment Required FCC ComplianceSupport Information Unpacking Instructions Hardware PreparationHardware Preparation and Installation VMEbus Connector P1 Configuration Switches Switch S1Configuration Switch S1 General Information S1-1 to S1-8 OFF -- All Ones Factory Configuration Installation Instructions Switch S6Connectors MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Controls and Indicators Abort Switch S2Reset Switch S3 Front Panel Indicators DS1-DS6 Memory MapsProcessor Bus Memory Map Processor Bus Memory Map Address Range Devices Accessed Port Size Local Devices Memory MapDetailed I/O Memory Maps 108 BusSwitch Register Memory Map100 110Memory Maps Ecdm CSR Register Memory Map ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTERDcam I2C Base Address = $C0 default Offset Dcam I2C Register Memory MapOperating Instructions VMEchip2 Memory Map Sheet 1 OffsetOperating Instructions Global Access BUS Watchdog Timeout Prescaler Adjust VMEchip2 Memory Map Sheet 2Operating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Memory Map Sheet 4 VMEchip2 Gcsr Base Address = $FFF40100Operating Instructions PCCchip2 Memory Map Printer PE Interrupt Control Register $FFF42033 Printer Fault Interrupt Control Register $FFF42031Printer SEL Interrupt Control Register $FFF42032 Printer Busy Interrupt Control Register $FFF42034Cirrus Logic CD2400 Memory Map Offsets Size Access Cirrus Logic CD2401 Serial Port Memory MapBase Address Is $FFF45000 Data Bits Address D31 D16 D15 12. MK48T08 BBRAM, TOD Clock Memory Map Accesses may be 8-bit or 32-bit, but not 16-bit11 C710 Scsi Memory Map Address Range Description Size Bytes13. Bbram Configuration Area Memory Map 14. TOD Clock Memory MapData Bits Address Function BBRAM, TOD Clock Memory Map 0460000000470476 01-W3869B03A VMEbus Accesses to the Local Peripheral BusVMEbus Memory Map 5000Local Reset Operation Software InitializationMulti-MPU Programming Considerations User’s Manual MVME197LE Functional Description Data Bus StructureMC88110 MPU Functional Description Mezzanine Address Bus Bus Data Bus 256 BusSwitchMC88110 Address Data MUX Address Memory ArrayBattery Backup RAM and Clock Flash MemoryOnboard Dram VMEbus Interface InterfacesSerial Port Interface Printer Interface Ethernet InterfaceScsi Interface Programmable Tick TimersPeripheral Resources Scsi TerminationLocal Peripheral Bus Timeout Watchdog TimerProcessor Bus Timeout Interrupt SourcesMVME197LE/D2 Functional Description EIA-232-D Interconnections Pin Signal Signal Name and Description Number Mnemonic Table A-1. EIA-232-D InterconnectionsRing Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Index NumericsIN-2 IN-3 Index

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