Motorola user manual MVME197LE Functional Description, Data Bus Structure, MC88110 MPU

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FUNCTIONAL DESCRIPTION

4

Introduction

This chapter provides a block diagram level description of the MVME197LE Single Board Computer. The functional description provides an overview of the module, followed by a detailed description of several blocks of the module. The block diagram for the MVME197LE is illustrated in Figure 4-1.

Descriptions of the other blocks of the MVME197LE module, including programmable registers in the ASICs and peripheral chips, are given in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide. Refer to it for the rest of the functional description of the MVME197LE module.

MVME197LE Functional Description

The MVME197LE module is a high functionality VMEbus single board computer based on the MC88110 second generation RISC microprocessor. The MVME197LE has 32/64MB of DRAM, 1MB of FLASH memory, 128/256KB of BOOT ROM, 8KB of static RAM (with battery backup), a time of day clock (with battery backup), an Ethernet transceiver interface, four serial ports with EIA-232-D interface, six tick timers, a watchdog timer, a SCSI bus interface with DMA (Direct Memory Access), a Centronics printer port, an A16/A24/ A32/D8/D16/D32 VMEbus master/slave interface, and a VMEbus system controller.

Data Bus Structure

The local data bus on the MVME197LE module is designed to accommodate the various 8-bit, 16-bit, and 32-bit devices that reside on the module. Refer to the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide and to the specific sections of this user’s manual for each device to determine its port size, the data bus connection, and any restrictions that apply when accessing the specific device.

MC88110 MPU

The MVME197LE is based on the MC88000 family and uses one MC88110 RISC microprocessor unit. Refer to the MC88110 Second Generation RISC Microprocessor User’s Manual for more information.

MVME197LE/D24-1

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Contents MVME197LE/D2 MVME197LERestricted Rights Legend Document Terminology PrefaceBIT Document Title Motorola Publication Number Related DocumentationPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv General Description IntroductionOte FeaturesCharacteristics Specifications SpecificationsMVME197LE Specifications Cooling Requirements FCC Compliance Equipment RequiredSupport Information Hardware Preparation Unpacking InstructionsHardware Preparation and Installation VMEbus Connector P1 Configuration Switch S1 General Information Configuration SwitchesSwitch S1 S1-1 to S1-8 OFF -- All Ones Factory Configuration Connectors Installation InstructionsSwitch S6 MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Reset Switch S3 Controls and IndicatorsAbort Switch S2 Processor Bus Memory Map Front Panel Indicators DS1-DS6Memory Maps Processor Bus Memory Map Local Devices Memory Map Address Range Devices Accessed Port SizeDetailed I/O Memory Maps 110 BusSwitch Register Memory Map100 108Memory Maps ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTER Ecdm CSR Register Memory MapDcam I2C Register Memory Map Dcam I2C Base Address = $C0 default OffsetOperating Instructions Offset VMEchip2 Memory Map Sheet 1Operating Instructions VMEchip2 Memory Map Sheet 2 Global Access BUS Watchdog Timeout Prescaler AdjustOperating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Gcsr Base Address = $FFF40100 VMEchip2 Memory Map Sheet 4Operating Instructions PCCchip2 Memory Map Printer Busy Interrupt Control Register $FFF42034 Printer Fault Interrupt Control Register $FFF42031Printer SEL Interrupt Control Register $FFF42032 Printer PE Interrupt Control Register $FFF42033Base Address Is $FFF45000 Cirrus Logic CD2400 Memory Map Offsets Size AccessCirrus Logic CD2401 Serial Port Memory Map Data Bits Address D31 D16 D15 Address Range Description Size Bytes Accesses may be 8-bit or 32-bit, but not 16-bit11 C710 Scsi Memory Map 12. MK48T08 BBRAM, TOD Clock Memory MapData Bits Address Function 13. Bbram Configuration Area Memory Map14. TOD Clock Memory Map 000000470476 BBRAM, TOD Clock Memory Map0460 5000 VMEbus Accesses to the Local Peripheral BusVMEbus Memory Map 01-W3869B03AMulti-MPU Programming Considerations Local Reset OperationSoftware Initialization User’s Manual MC88110 MPU MVME197LE Functional DescriptionData Bus Structure Functional Description Memory Array Bus Data Bus 256 BusSwitchMC88110 Address Data MUX Address Mezzanine Address BusOnboard Dram Battery Backup RAM and ClockFlash Memory Serial Port Interface VMEbus InterfaceInterfaces Ethernet Interface Printer InterfaceScsi Termination Programmable Tick TimersPeripheral Resources Scsi InterfaceInterrupt Sources Watchdog TimerProcessor Bus Timeout Local Peripheral Bus TimeoutMVME197LE/D2 Functional Description EIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Signal Name and Description Number MnemonicRing Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Numerics IndexIN-2 IN-3 Index

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