Motorola MVME197LE Memory Maps, Front Panel Indicators DS1-DS6, Processor Bus Memory Map

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Operating Instructions

by a control bit in the LCSR. SYSRESET* remains asserted for at least 200 msec, as required by the VMEbus specification.

Similarly, the VMEchip2 provides an input signal and a control bit to initiate

3a local reset operation. By setting a control bit, software can maintain a board in a reset state, disabling a faulty board from participating in normal system operation.

The local reset driver is enabled even when the VMEchip2 is not the system controller. A local reset may be generated by the RESET switch, a power up reset, a watchdog timeout, a VMEbus SYSRESET*, or a control bit in the GCSR.

Front Panel Indicators (DS1-DS6)

The six LEDs on the MVME197LE front panel are: FAIL, SCON, RUN, LAN, VME, and SCSI.

1.The yellow FAIL LED (DS1) is lit when the BRDFAIL signal line is active.

2.The green SCON LED (DS2) is lit when the VMEchip2 is the VMEbus system controller.

3.The green RUN LED (DS3) is lit when the MC88110 bus MC* pin is low.

4.The green LAN LED (DS4) lights when the LAN chip is the local peripheral bus master.

5.The green VME LED (DS5) lights when the board is using the VMEbus or when the board is accessed by the VMEbus.

6.The green SCSI LED (DS6) lights when the SCSI chip is the local peripheral bus master.

Memory Maps

There are three points of view for the memory maps: 1) the mapping of all resources as viewed by the Processor Bus (MC88110 bus), 2) the mapping of onboard/off-board resources as viewed from the Local Peripheral Bus (MC68040 compatible bus), and 3) the mapping of onboard resources as viewed by VMEbus Masters (VMEbus memory map).

Processor Bus Memory Map

Care should be taken, since all three maps are programmable. It is recommended that direct mapping from the Processor Bus to the Local Peripheral Bus be used.

3-2	User’s Manual

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Contents MVME197LE MVME197LE/D2Restricted Rights Legend Preface Document TerminologyBIT Related Documentation Document Title Motorola Publication NumberPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv Introduction General DescriptionFeatures OteCharacteristics Specifications SpecificationsMVME197LE Specifications Cooling Requirements Equipment Required FCC ComplianceSupport Information Unpacking Instructions Hardware PreparationHardware Preparation and Installation VMEbus Connector P1 Configuration Switch S1 General Information Configuration SwitchesSwitch S1 S1-1 to S1-8 OFF -- All Ones Factory Configuration Connectors Installation InstructionsSwitch S6 MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Reset Switch S3 Controls and IndicatorsAbort Switch S2 Processor Bus Memory Map Front Panel Indicators DS1-DS6Memory Maps Processor Bus Memory Map Address Range Devices Accessed Port Size Local Devices Memory MapDetailed I/O Memory Maps BusSwitch Register Memory Map 100108 110Memory Maps Ecdm CSR Register Memory Map ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTERDcam I2C Base Address = $C0 default Offset Dcam I2C Register Memory MapOperating Instructions VMEchip2 Memory Map Sheet 1 OffsetOperating Instructions Global Access BUS Watchdog Timeout Prescaler Adjust VMEchip2 Memory Map Sheet 2Operating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Memory Map Sheet 4 VMEchip2 Gcsr Base Address = $FFF40100Operating Instructions PCCchip2 Memory Map Printer Fault Interrupt Control Register $FFF42031 Printer SEL Interrupt Control Register $FFF42032Printer PE Interrupt Control Register $FFF42033 Printer Busy Interrupt Control Register $FFF42034Base Address Is $FFF45000 Cirrus Logic CD2400 Memory Map Offsets Size AccessCirrus Logic CD2401 Serial Port Memory Map Data Bits Address D31 D16 D15 Accesses may be 8-bit or 32-bit, but not 16-bit 11 C710 Scsi Memory Map12. MK48T08 BBRAM, TOD Clock Memory Map Address Range Description Size BytesData Bits Address Function 13. Bbram Configuration Area Memory Map14. TOD Clock Memory Map 000000470476 BBRAM, TOD Clock Memory Map0460 VMEbus Accesses to the Local Peripheral Bus VMEbus Memory Map01-W3869B03A 5000Multi-MPU Programming Considerations Local Reset OperationSoftware Initialization User’s Manual MC88110 MPU MVME197LE Functional DescriptionData Bus Structure Functional Description Bus Data Bus 256 BusSwitch MC88110 Address Data MUX AddressMezzanine Address Bus Memory ArrayOnboard Dram Battery Backup RAM and ClockFlash Memory Serial Port Interface VMEbus InterfaceInterfaces Printer Interface Ethernet InterfaceProgrammable Tick Timers Peripheral ResourcesScsi Interface Scsi TerminationWatchdog Timer Processor Bus TimeoutLocal Peripheral Bus Timeout Interrupt SourcesMVME197LE/D2 Functional Description EIA-232-D Interconnections Pin Signal Signal Name and Description Number Mnemonic Table A-1. EIA-232-D InterconnectionsRing Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Index NumericsIN-2 IN-3 Index

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