Motorola MVME197LE user manual Bit

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Data and address sizes are defined as follows:

❏A byte is eight bits, numbered 0 through 7, with bit 0 being the least significant.

❏A two-byte is 16 bits, numbered 0 through 15, with bit 0 being the least significant. For the MVME197series and other RISC modules, this is called a half-word.

❏A four-byte is 32 bits, numbered 0 through 31, with bit 0 being the least significant. For the MVME197 series and other RISC modules, this is called a word.

❏An eight-byte is 64 bits, numbered 0 through 63, with bit 0 being the least significant. For the MVME197 series and other RISC modules, this is called a double-word.

Throughout this document, it is assumed that the MPU on the MVME197 module series is always programmed with big-endian byte ordering, as shown below. Any attempt to use small-endian byte ordering will immediately render the MVME197Bug debugger unusable.

BIT							BIT
63	56	55	48	47	40	39	32

ADRO		ADR1		ADR2			ADR3

31	24	23	16	15	08	07	00

ADR4		ADR5		ADR6			ADR7

The terms control bit and status bit are used extensively in this document. The term control bit is used to describe a bit in a register that can be set and cleared under software control. The term true is used to indicate that a bit is in the state that enables the function it controls. The term false is used to indicate that the bit is in the state that disables the function it controls. In all tables, the terms 0 and 1 are used to describe the actual value that should be written to the bit, or the value that it yields when read. The term status bit is used to describe a bit in a register that reflects a specific condition. The status bit can be read by software to determine operational or exception conditions.

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Contents MVME197LE MVME197LE/D2Restricted Rights Legend Preface Document TerminologyBIT Related Documentation Document Title Motorola Publication NumberPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv Introduction General DescriptionFeatures OteMVME197LE Specifications SpecificationsCharacteristics Specifications Cooling Requirements Equipment Required FCC ComplianceSupport Information Unpacking Instructions Hardware PreparationHardware Preparation and Installation VMEbus Connector P1 Switch S1 Configuration SwitchesConfiguration Switch S1 General Information S1-1 to S1-8 OFF -- All Ones Factory Configuration Switch S6 Installation InstructionsConnectors MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Abort Switch S2 Controls and IndicatorsReset Switch S3 Memory Maps Front Panel Indicators DS1-DS6Processor Bus Memory Map Processor Bus Memory Map Address Range Devices Accessed Port Size Local Devices Memory MapDetailed I/O Memory Maps BusSwitch Register Memory Map 100108 110Memory Maps Ecdm CSR Register Memory Map ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTERDcam I2C Base Address = $C0 default Offset Dcam I2C Register Memory MapOperating Instructions VMEchip2 Memory Map Sheet 1 OffsetOperating Instructions Global Access BUS Watchdog Timeout Prescaler Adjust VMEchip2 Memory Map Sheet 2Operating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Memory Map Sheet 4 VMEchip2 Gcsr Base Address = $FFF40100Operating Instructions PCCchip2 Memory Map Printer Fault Interrupt Control Register $FFF42031 Printer SEL Interrupt Control Register $FFF42032Printer PE Interrupt Control Register $FFF42033 Printer Busy Interrupt Control Register $FFF42034Cirrus Logic CD2401 Serial Port Memory Map Cirrus Logic CD2400 Memory Map Offsets Size AccessBase Address Is $FFF45000 Data Bits Address D31 D16 D15 Accesses may be 8-bit or 32-bit, but not 16-bit 11 C710 Scsi Memory Map12. MK48T08 BBRAM, TOD Clock Memory Map Address Range Description Size Bytes14. TOD Clock Memory Map 13. Bbram Configuration Area Memory MapData Bits Address Function 0460 BBRAM, TOD Clock Memory Map000000470476 VMEbus Accesses to the Local Peripheral Bus VMEbus Memory Map01-W3869B03A 5000Software Initialization Local Reset OperationMulti-MPU Programming Considerations User’s Manual Data Bus Structure MVME197LE Functional DescriptionMC88110 MPU Functional Description Bus Data Bus 256 BusSwitch MC88110 Address Data MUX AddressMezzanine Address Bus Memory ArrayFlash Memory Battery Backup RAM and ClockOnboard Dram Interfaces VMEbus InterfaceSerial Port Interface Printer Interface Ethernet InterfaceProgrammable Tick Timers Peripheral ResourcesScsi Interface Scsi TerminationWatchdog Timer Processor Bus TimeoutLocal Peripheral Bus Timeout Interrupt SourcesMVME197LE/D2 Functional Description EIA-232-D Interconnections Pin Signal Signal Name and Description Number Mnemonic Table A-1. EIA-232-D InterconnectionsRing Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Index NumericsIN-2 IN-3 Index

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