Motorola MVME197LE user manual Appendix a

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Processor Bus Memory Map		3-2
	Detailed I/O Memory Maps	3-5
	BBRAM, TOD Clock Memory Map	3-19
VMEbus Memory Map		3-20
	VMEbus Accesses to the Local Peripheral Bus	3-20
	VMEbus Short I/O Memory Map	3-20
Software Initialization		3-21
Multi-MPU Programming Considerations		3-21
Local Reset Operation		3-21
CHAPTER 4	FUNCTIONAL DESCRIPTION
Introduction		4-1
MVME197LE Functional Description		4-1
Data Bus Structure		4-1
MC88110 MPU		4-1
BOOT ROM		4-3
FLASH Memory		4-3
Onboard DRAM		4-3
Battery Backup RAM and Clock		4-3
VMEbus Interface		4-4
I/O Interfaces		4-4
	Serial Port Interface	4-4
	Printer Interface	4-5
	Ethernet Interface	4-5
	SCSI Interface	4-6
	SCSI Termination	4-6
Peripheral Resources		4-6
	Programmable Tick Timers	4-6
	Watchdog Timer	4-7
	Software-Programmable Hardware Interrupts	4-7
	Processor Bus Timeout	4-7
	Local Peripheral Bus Timeout	4-7
Interrupt Sources		4-7
APPENDIX A	EIA-232-D INTERCONNECTIONS	A-1

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Contents MVME197LE MVME197LE/D2Restricted Rights Legend Preface Document TerminologyBIT Related Documentation Document Title Motorola Publication NumberPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv Introduction General DescriptionFeatures OteMVME197LE Specifications SpecificationsCharacteristics Specifications Cooling Requirements Equipment Required FCC ComplianceSupport Information Unpacking Instructions Hardware PreparationHardware Preparation and Installation VMEbus Connector P1 Switch S1 Configuration SwitchesConfiguration Switch S1 General Information S1-1 to S1-8 OFF -- All Ones Factory Configuration Switch S6 Installation InstructionsConnectors MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Abort Switch S2 Controls and IndicatorsReset Switch S3 Memory Maps Front Panel Indicators DS1-DS6Processor Bus Memory Map Processor Bus Memory Map Address Range Devices Accessed Port Size Local Devices Memory MapDetailed I/O Memory Maps 108 BusSwitch Register Memory Map100 110Memory Maps Ecdm CSR Register Memory Map ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTERDcam I2C Base Address = $C0 default Offset Dcam I2C Register Memory MapOperating Instructions VMEchip2 Memory Map Sheet 1 OffsetOperating Instructions Global Access BUS Watchdog Timeout Prescaler Adjust VMEchip2 Memory Map Sheet 2Operating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Memory Map Sheet 4 VMEchip2 Gcsr Base Address = $FFF40100Operating Instructions PCCchip2 Memory Map Printer PE Interrupt Control Register $FFF42033 Printer Fault Interrupt Control Register $FFF42031Printer SEL Interrupt Control Register $FFF42032 Printer Busy Interrupt Control Register $FFF42034Cirrus Logic CD2401 Serial Port Memory Map Cirrus Logic CD2400 Memory Map Offsets Size AccessBase Address Is $FFF45000 Data Bits Address D31 D16 D15 12. MK48T08 BBRAM, TOD Clock Memory Map Accesses may be 8-bit or 32-bit, but not 16-bit11 C710 Scsi Memory Map Address Range Description Size Bytes14. TOD Clock Memory Map 13. Bbram Configuration Area Memory MapData Bits Address Function 0460 BBRAM, TOD Clock Memory Map000000470476 01-W3869B03A VMEbus Accesses to the Local Peripheral BusVMEbus Memory Map 5000Software Initialization Local Reset OperationMulti-MPU Programming Considerations User’s Manual Data Bus Structure MVME197LE Functional DescriptionMC88110 MPU Functional Description Mezzanine Address Bus Bus Data Bus 256 BusSwitchMC88110 Address Data MUX Address Memory ArrayFlash Memory Battery Backup RAM and ClockOnboard Dram Interfaces VMEbus InterfaceSerial Port Interface Printer Interface Ethernet InterfaceScsi Interface Programmable Tick TimersPeripheral Resources Scsi TerminationLocal Peripheral Bus Timeout Watchdog TimerProcessor Bus Timeout Interrupt SourcesMVME197LE/D2 Functional Description EIA-232-D Interconnections Pin Signal Signal Name and Description Number Mnemonic Table A-1. EIA-232-D InterconnectionsRing Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Index NumericsIN-2 IN-3 Index

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