CHAPTER 5: Peripheral Operation
5.3.2CONTROLLED BUS DATA TRANSFERS
If the controller must avoid waiting for the serial device, it can
When
Another bit (DIO4) of the Serial Poll byte is used to indicate additional information concerning the IEEE input buffer. This bit is set to a logic “1” when there is 1280 or less locations in the buffer for data. It is cleared, set to a logic “0”, when there is greater than 1280 locations available. This bit is referred to as the IEEE input buffer FULL bit.
When serial data is received, DIO5 of the Serial Poll byte is set to “1”, to indicate to the IEEE controller that the serial input buffer is NOT EMPTY. If this bit is set, it indicates that at least one character is available in the serial input buffer to be read by the IEEE controller. Once all of the serial input data is read by the IEEE controller this bit is reset.
The interface converter can generate a request for service on the bus when it receives the last serial terminator. To enable this feature, the Peripheral SRQ switch, located on the internal switch bank of SW1, must be enabled. When SRQ is enabled, the interface converter will assert the IEEE bus SRQ line and set serial poll status bits DIO7 and DIO3 when the last serial terminator is detected. The IEEE controller must perform a serial poll on the interface to clear the SRQ. If the Peripheral SRQ switch is in the disabled position, there will not be any indication in the
47