Agilent Technologies FS2334 user manual Test Points

Page 10

FS2334 Frontside layout

Header 3	Header 4	Header 5
				Header 1			Header 7	Header 8
				Header 1		Header 6	Header 7	Header 8

1.25”

Header 14

FS2334 Backside layout

		TP 5
		TP 5					Header 2
							Header 2

Header 13										Header 11 Header 10 Header 12


								TP 1,2,3,7
				Header 9

TP 6		TP 4

Test Points

There are several test point on the board.

The first set of test points are used to select which signals go to the Clk input and the D15 input of Header 2. The shipping configuration for the FS2334 is to have S0 wired to the Clk input, which is TP3 wired to TP2. This is done in the factory by soldering a short wire between the 2 test points.

If CKE0 is to be used as a Clk input then TP7 is wired to TP2 and S0 is brought to the

D15 input by wiring TP3 to TP1.

DM2_DQS11 is not brought to the logic analyzer, but it can be probed at TP4

DQS5n is not brought to the logic analyzer, but it can be probed at TP5

DQS14n is not brought to the logic analyzer, but it can be probed at TP6

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Contents DDR2 Dimm High Speed Probe FS2334 Product Warranty Appendix For Technical Support For Sales and Marketing SupportProduct Warranty Exclusive RemediesSoftware License Agreement Introduction DefinitionsFS2334 Probe Description Probe Technical Feature SummaryProbe Components Signal Threshold Voltage Settings Signal Assignments on Probe PodsConnecting the DDR2 Probe to the Logic Analyzer Test Points Signal Isolation on the Probe Connecting to your Target SystemBuffered signals on the probe Write state analysis Page Software Requirements Setting up the 169xx Analyzer169xx Licensing Offline Analysis Page TimingZoom Analysis Decoding DDR CommandsTaking a Trace, Triggering, and Seeing Measurement Results State Analysis OverviewState Analysis Operation Read and Write at 667MT/s or slower Process for setting sampling positions at speeds of 800MT/s State analysis calibration procedure Page Page Adjusting the sampling positions with controlled stimulus Page State Display FS1140 Installation and Licensing Loading the FS1140Setting up the FS1140 DDR2 Tool Statistics Export Timing AnalysisPage Header 1 Command AppendixDP16P/ CLK CK0 Header 2 Command NC3 Header 3 Write DQ9 Header 4 Write Ground D13 DQ22 20K ohm to D14 DQ18 D15 DQ23 Header 5 Write CB0 CB1 20K ohm to Ground D13 No connection D14 D15 Header 6 Write DM5DQS14 Header 7 -Write 20K ohm to Ground D13 DQ50 D14 DQ55 D15 DQ51 Header 8 Write SDA Header 12 Read Duplicates only data signals 20K ohm to Ground D15 No connection Header 10 Read Duplicates only data signals DP16P/ CLK CB7 Header 11 Read Duplicates only data signals DP16P/ CLK RAS Header 9 Read Duplicates only data signals DP16P/ CLK CK2 Header 13 Read Duplicates only data signals Ground D13 DQ50 20K ohm to D14 DQ55 D15 DQ51