Adjusting the sampling positions with controlled stimulus
This is a special case requiring special stimulus of the DDR2 DIMM bus. This may involve the use of a special memory test card from
•The Auto Sample Position Setup and Auto Threshold functions of the Agilent logic analyzer are the most precise method of determining the data valid window for signals and then setting each logic analyzer sample position to that optimum value for state analysis. There are several basic concepts that should be understood first. In order to run Auto Sample Position Setup and Auto Threshold on the Data signals it is important that the target system is programmed to generate exclusively Write or Read traffic. This is the only way to get usable data windows to set the sampling positions of both the Read and Write Data labels on the logic analyzer. At these speeds even ½ a data strobe bit width of timing relationship shift between the strobe (clock) and the data bits will eliminate the window.
•The Threshold setting for clocks and signals can have a significant effect on the size of the eyes. At speeds of 667MT/s or higher even a 50mV change in the threshold can make all the difference in the eye size as measured at the logic analyzer. The best way to determine this level is through trial and error, or through use of the Auto Threshold function.
•The Command/Address/Control signals are all qualified by Chip Select (S0:1), and therefore one of these signals should be used as a clock qualifier when using Eyefinder to set sampling positions. However, 600MHz State speed on the Agilent logic analyzer does not provide clock qualification. You can set the sampling speed to 300MHz and slow the system DDR clock down to 333MHz (667MT/s) and run Eyefinder on the Command/Address/Control signals with the S0 clock qualification. Set the sampling speed and system DDR clock back afterwards. Alternatively, the use of a special memory test may provide a mode where there are continuous Chip Select qualified commands at 800MT/s
1.To setup the sampling positions for Address, Command and Control signals. This can be done using a Timing or State configuration as they use CK0 as the clock input for the logic analyzer. Make sure the Clock mode is Rising edge. Set the Sampling Options to 300MHz and select S0 as a Clock Qualifier – Low, (refer to section on secondary Clock inputs). Generate some bus traffic and run Auto Sample Position Setup and/or Auto Threshold as required to establish correct Threshold settings, valid eye openings, and sample positions for these signals. NOTE: You have to have the target system running at 667MT/s for this process.
2.For Data signal sample positions, initiate traffic on the target system that generates as much only Write bursts to the DIMM as possible. If there are Read bursts contained in this traffic the positions of the Data signal edges change relative Clock input and this will close the valid eye openings for all the Data signals. All Clock cycles that occur without Write Data transfers will also close down the eyes. Run Auto Sample Position Setup and/or Auto Threshold as required to establish correct Threshold settings, valid eye openings, and sample positions for these signals. Move the sample positions for the Data Strobes and all the Data labels (rising and falling) to the center of the valid windows for those labels as shown below.
3.Initiate traffic on the target system that generates only Read bursts to the DIMM. If there are Write bursts contained in this traffic the positions of the Data
24