Agilent Technologies FS2334 user manual State analysis calibration procedure

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State analysis calibration procedure

This process is in large part the same for both use in the 7 card Read and Write configuration at 800MT/s and for the 4 card configurations. Differences are noted.

1)Start a memory test program that creates a good mixture of reads and writes in a single TimingZoom trace. A trigger on a write may be required if the test program does not have a mix or reads and writes in close proximity.

Note that in addition to looking for the DDR commands the #S0:1 and CKE0:1 signals are used to determine if the command is actually addressing a memory chip. The Write – Command:CK2_TZ signal is used to make sure the command is sampled on the rising edge of the DIMM clock (since that is when the DDR command bus is valid).

2)Bring up a waveform display and add the TimingZoom labels for the command clock, chip selects, and DQS0 (Write – Command:CK2_TZ, #S0_TZ, DQS8-

0_TZ[0]) and the data bus labels for Writes (Data63-32_R/Fand Data31-0_R/F) in the waveform view. Scroll the waveforms to find the start of a Write burst. You will see this by finding where the DQS0 strobe becomes active.

Note: The 4 card configurations have only 2 sets of Data labels.

3)Now the time delay from the closest rising edge of Write – Command:CK2_TZ prior to the center of the write data eyes can be measured. This will be the DATA_rising point. Place a marker on that edge of the Write – Command:CK2_TZ. Place the other marker in the center of the data valid region for the data label. You may find it easier to identify this point by locating the point on one of the DQS signals that is equal distances from the edges. Note the 103 ps delay between the markers as shown below.

The 4 card config for 667MT/s will use delays measured from the nearest rising of falling edge of the state clock.

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Contents DDR2 Dimm High Speed Probe FS2334 Product Warranty Appendix For Sales and Marketing Support For Technical SupportExclusive Remedies Product WarrantySoftware License Agreement Definitions IntroductionProbe Technical Feature Summary FS2334 Probe DescriptionProbe Components Signal Assignments on Probe Pods Signal Threshold Voltage SettingsConnecting the DDR2 Probe to the Logic Analyzer Test Points Connecting to your Target System Signal Isolation on the ProbeBuffered signals on the probe Write state analysis Page Setting up the 169xx Analyzer Software Requirements169xx Licensing Offline Analysis Page Decoding DDR Commands TimingZoom AnalysisTaking a Trace, Triggering, and Seeing Measurement Results Overview State AnalysisState Analysis Operation Read and Write at 667MT/s or slower Process for setting sampling positions at speeds of 800MT/s State analysis calibration procedure Page Page Adjusting the sampling positions with controlled stimulus Page State Display Loading the FS1140 FS1140 Installation and LicensingSetting up the FS1140 DDR2 Tool Statistics Timing Analysis ExportPage Appendix Header 1 CommandDP16P/ CLK CK0 Header 2 Command NC3 Header 3 Write DQ9 Header 4 Write Ground D13 DQ22 20K ohm to D14 DQ18 D15 DQ23 Header 5 Write CB0 CB1 20K ohm to Ground D13 No connection D14 D15 Header 6 Write DM5DQS14 Header 7 -Write 20K ohm to Ground D13 DQ50 D14 DQ55 D15 DQ51 Header 8 Write SDA Header 12 Read Duplicates only data signals 20K ohm to Ground D15 No connection Header 10 Read Duplicates only data signals DP16P/ CLK CB7 Header 11 Read Duplicates only data signals DP16P/ CLK RAS Header 9 Read Duplicates only data signals DP16P/ CLK CK2 Header 13 Read Duplicates only data signals Ground D13 DQ50 20K ohm to D14 DQ55 D15 DQ51
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