Agilent Technologies FS2334 Signal Assignments on Probe Pods, Signal Threshold Voltage Settings

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Signal Assignments on Probe Pods

The overlap in the bit ranges (for DQxx) signals between pods occurs because the bits are assigned to pods in the order that they appear physically on the DDR2 DIMM connector, which is not strictly in logical bit order. This allows the Probe layout to better match stub lengths among all DQxx signals.

See the Appendix for a detailed list of how Logic Analyzer Channels are mapped to signals and DDR2 pins.

Signal Threshold Voltage Settings

The standard voltage threshold for the logic analyzer pods is defined as 900mV. This is based on the SSTL2-1.8V signaling used by the DDR2 DIMM bus. The configuration files provided with this product set-up the threshold voltages for both the Data and Command pods to 900mV. Design differences between target platforms or overvoltage settings may require adjustment of the logic analyzers threshold for optimal signal capture. The use of Eye Scan can be very helpful in determining where to set these thresholds.

NOTE: The optimal settings may need to be defined either through trial and error or by using Eye Scan. Accurate data capture is very dependent on optimizing these settings and changes of as little as 50mV may have a significant effect.

Connecting the DDR2 Probe to the Logic Analyzer

The FS2334 DDR2 Probe requires up to 7 logic analyzer cards depending on whether state (Read and Write - quadruple sampled), state (Read or Write - dual sampled), or timing measurements are desired. See Timing and State configuration information below.

At this time the user may find it easier to connect the logic analyzer cables to the probe before inserting the probe into the target system. The FS2334 probe has fourteen 90 pin pod connections which mate directly to Agilent Logic analyzer cards. Adapter cables are not required. Once a configuration file is loaded refer to the General Purpose Probe feature in the Agilent 1690x Overview tab for cable connections.

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Contents DDR2 Dimm High Speed Probe FS2334 Product Warranty Appendix For Sales and Marketing Support For Technical SupportExclusive Remedies Product WarrantySoftware License Agreement Definitions IntroductionProbe Technical Feature Summary FS2334 Probe DescriptionProbe Components Signal Assignments on Probe Pods Signal Threshold Voltage SettingsConnecting the DDR2 Probe to the Logic Analyzer Test Points Connecting to your Target System Signal Isolation on the ProbeBuffered signals on the probe Write state analysis Page Setting up the 169xx Analyzer Software Requirements169xx Licensing Offline Analysis Page Decoding DDR Commands TimingZoom AnalysisTaking a Trace, Triggering, and Seeing Measurement Results Overview State AnalysisState Analysis Operation Read and Write at 667MT/s or slower Process for setting sampling positions at speeds of 800MT/s State analysis calibration procedure Page Page Adjusting the sampling positions with controlled stimulus Page State Display Loading the FS1140 FS1140 Installation and LicensingSetting up the FS1140 DDR2 Tool Statistics Timing Analysis ExportPage Appendix Header 1 CommandDP16P/ CLK CK0 Header 2 Command NC3 Header 3 Write DQ9 Header 4 Write Ground D13 DQ22 20K ohm to D14 DQ18 D15 DQ23 Header 5 Write CB0 CB1 20K ohm to Ground D13 No connection D14 D15 Header 6 Write DM5DQS14 Header 7 -Write 20K ohm to Ground D13 DQ50 D14 DQ55 D15 DQ51 Header 8 Write SDA Header 12 Read Duplicates only data signals 20K ohm to Ground D15 No connection Header 10 Read Duplicates only data signals DP16P/ CLK CB7 Header 11 Read Duplicates only data signals DP16P/ CLK RAS Header 9 Read Duplicates only data signals DP16P/ CLK CK2 Header 13 Read Duplicates only data signals Ground D13 DQ50 20K ohm to D14 DQ55 D15 DQ51
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