Agilent Technologies FS2334 Process for setting sampling positions at speeds of 800MT/s

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The process for setting sampling positions at speeds of 800MT/s:

This procedure requires the probe user to capture TimingZoom traces and use the markers to determine the correct sampling positions. This is an iterative, trial and error procedure where adjustments to Data signal sampling positions may need to be adjusted several times before they provide correct State data capture on both Read and Writes.

When operating at 800MT/s data speed and a Multi-Frame configuration. There are several things to consider:

1) There are 4 sets of State Data. These are:

 

a. Write Data sampled on the rising edge of CK0

Data63-0_R

b. Write Data sampled on the falling edge of CK0

Data63-0_F

c. Read Data sampled on the rising edge of CK2

READdata63-0_R

d. Read Data sampled on the falling edge of CK2

READdata63-0_F

2)Please note within each of these 4 groups of labels there are additional labels organized by data byte. This is because many platforms may display timing differences between byte groups and therefore require a slightly different sampling setting which the byte labels make easier to both measure and set.

3)At 400MHz clock speed the 16900 analyzer in this configuration will display both the State and TimingZoom version of the State Clock signal, (CommandClk) CK0 for the Write analyzer and CK2 for the Read analyzer, at ½ it’s actual frequency. For an

.actual representation of the state clock use Write – Command:CK2_TZ

4)Because of the logic analyzer’s pod to pod skew of +/- 1.75ns, you want to take several timing offset measurements before setting a sampling value.

5)Both the Write and Read analyzers are clocked only on the rising edge of their State Clocks.

6)The Intermodule Skew should not need adjustment for State analysis. This can done if necessary by aligning the MRAS_TZ (Write analyzer) and RAS_TZ (Read analyzer) signals, but the user will have to reset it after every trace capture.

7)Sample positions for Command, Address and Control signals are already set to values that should allow proper State analysis. If adjustment is necessary they can be moved using either the TimingZoom measurement procedure described here, or by using Auto Sample positioning provided that Chip Select qualification is applied or the system is slowed down to a DDR clock rate of 333MHz and the logic analyzer is set to 300MHz State mode.

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Contents DDR2 Dimm High Speed Probe FS2334 Product Warranty Appendix For Technical Support For Sales and Marketing SupportProduct Warranty Exclusive RemediesSoftware License Agreement Introduction DefinitionsProbe Components Probe Technical Feature SummaryFS2334 Probe Description Connecting the DDR2 Probe to the Logic Analyzer Signal Assignments on Probe PodsSignal Threshold Voltage Settings Test Points Buffered signals on the probe Connecting to your Target SystemSignal Isolation on the Probe Write state analysis Page 169xx Licensing Setting up the 169xx AnalyzerSoftware Requirements Offline Analysis Page Taking a Trace, Triggering, and Seeing Measurement Results Decoding DDR CommandsTimingZoom Analysis State Analysis OverviewState Analysis Operation Read and Write at 667MT/s or slower Process for setting sampling positions at speeds of 800MT/s State analysis calibration procedure Page Page Adjusting the sampling positions with controlled stimulus Page State Display FS1140 Installation and Licensing Loading the FS1140Setting up the FS1140 DDR2 Tool Statistics Export Timing AnalysisPage Header 1 Command AppendixDP16P/ CLK CK0 Header 2 Command NC3 Header 3 Write DQ9 Header 4 Write Ground D13 DQ22 20K ohm to D14 DQ18 D15 DQ23 Header 5 Write CB0 CB1 20K ohm to Ground D13 No connection D14 D15 Header 6 Write DM5DQS14 Header 7 -Write 20K ohm to Ground D13 DQ50 D14 DQ55 D15 DQ51 Header 8 Write SDA Header 12 Read Duplicates only data signals 20K ohm to Ground D15 No connection Header 10 Read Duplicates only data signals DP16P/ CLK CB7 Header 11 Read Duplicates only data signals DP16P/ CLK RAS Header 9 Read Duplicates only data signals DP16P/ CLK CK2 Header 13 Read Duplicates only data signals Ground D13 DQ50 20K ohm to D14 DQ55 D15 DQ51
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