Freescale Semiconductor DSP56366 manuals
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Freescale Semiconductor DSP56366 User Manual
366 pages 3.55 Mb
3 Contents15 List of Figures19 List of Tables21 Preface22 Manual ConventionsFreescale Semiconductor 1-1 25 1 DSP56366 Overview35 2 Signal/Connection Descriptions57 3 Memory Configuration3.1 Data and Program Memory MapsTable3-1 Internal Memory Configurations 58 Table3-2 On-chip RAM Memory LocationsTable3-3 On-chip ROM Memory LocationsFreescale Semiconductor 3-3 59 Figure 3-1 Memory Maps for MSW=(X,X), CE=0, MS=0, SC=0Figure 3-2 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=03-4 Freescale Semiconductor 60 Figure 3-3 Memory Maps for MSW=(0,0), CE=0 MS=1, SC=0Figure 3-4 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=0Freescale Semiconductor 3-5 61 Figure 3-5 Memory Maps for MSW=(1,0), CE=0, MS=1, SC=0Figure 3-6 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=03-6 Freescale Semiconductor 62 Figure 3-7 Memory Maps for MSW=(0,1), CE=1, MS=1, SC=0Figure 3-8 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=0DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 Freescale Semiconductor 3-7 63 Figure 3-9 Memory Maps for MSW=(X,X), CE=0, MS=0, SC=1Figure 3-10 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=13-8 Freescale Semiconductor 64 Figure 3-11 Memory Maps for MSW=(0,0), CE=0, MS=1, SC=1Figure 3-12 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=1Freescale Semiconductor 3-9 65 Figure 3-13 Memory Maps for MSW=(1,0), CE=0, MS=1, SC=1Figure 3-14 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=1DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4 3-10 Freescale Semiconductor 66 Figure 3-15 Memory Maps for MSW=(0,1), CE=1, MS=1, SC=1Figure 3-16 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=1 67 3.1.1 Reserved Memory Spaces3.1.2 Program ROM Area Reserved for Freescale Use 3.1.3 Bootstrap ROM 3.1.4 Dynamic Memory Configuration Switching 3.1.5 External Memory Support 68 3.2 Internal I/O Memory Map75 4 Core Configuration93 5 General Purpose Input/Output5.1 Introduction 5.2 P rogramming Model 95 6 Host Interface (HDI08)125 7 Serial Host Interface151 8 Enhanced Serial AUDIO Interface (ESAI)8.1 Introduction 153 8.2 E SAI Data and Control Pins157 8.3 E SAI Programming Model158 8.3.1 ESAI Transmitter Clock Control Register (TCCR)162 8.3.2 ESAI Transmit Control Register (TCR)172 8.3.3 ESAI Receive Clock Control Register (RCCR)176 8.3.4 ESAI Receive Control Register (RCR)177 8.3.4.1 RCR ESAI Receiver 0 Enable (RE0) - Bit 08.3.4.2 RCR ESAI Receiver 1 Enable (RE1) - Bit 1 8.3.4.3 RCR ESAI Receiver 2 Enable (RE2) - Bit 2 8.3.4.4 RCR ESAI Receiver 3 Enable (RE3) - Bit 3 8.3.4.5 RCR Reserved Bits - Bits 4-5, 17-18 8.3.4.6 RCR Receiver Shift Direction (RSHFD) - Bit 6 178 8.3.4.7 RCR Receiver Word Alignment Control (RWA) - Bit 78.3.4.8 RCR Receiver Network Mode Control (RMOD1-RMOD0) - Bits 8-9 8.3.4.9 RCR Receiver Slot and Word Select (RSWS4-RSWS0) - Bits 10-14 180 8.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 158.3.4.11 RCR Receiver Frame Sync Relative Timing (RFSR) - Bit 16 8.3.4.12 RCR Receiver Section Personal Reset (RPR) - Bit 19 8.3.4.13 RCR Receive Exception Interrupt Enable (REIE) - Bit 20 8.3.4.14 RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21 8.3.4.15 RCR Receive Interrupt Enable (RIE) - Bit 22 8.3.4.16 RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23 181 8.3.5 ESAI Common Control Register (SAICR)184 8.3.6 ESAI Status Register (SAISR)190 8.3.7 ESAI Receive Shift Registers8.3.8 ESAI Receive Data Registers (RX3, RX2, RX1, RX0) 8.3.9 ESAI Transmit Shift Registers 8.3.10 ESAI Transmit Data Registers (TX5, TX4, TX3, TX2,TX1,TX0) 8.3.11 ESAI Time Slot Register (TSR) 8.3.12 Transmit Slot Mask Registers (TSMA, TSMB) 192 8.3.13 Receive Slot Mask Registers (RSMA, RSMB)193 8.4 Operating Modes197 8.5 GPIO - Pins and Registers199 8.6 E SAI Initialization Examples201 9 Enhanced Serial Audio Interface 1 (ESAI_1)9.1 Introduction 203 9.2 ESAI_1 Data and Control Pins9.2.1 Serial Transmit 0 Data Pin (SDO0_1) 9.2.2 Serial Transmit 1 Data Pin (SDO1_1) 9.2.3 Serial Transmit 2/Receive 3 Data Pin (SDO2_1/SDI3_1) 9.2.4 Serial Transmit 3/Receive 2 Data Pin (SDO3_1/SDI2_1) 9.2.5 Serial Transmit 4/Receive 1 Data Pin (SDO4_1/SDI1_1) 9.2.6 Serial Transmit 5/Receive 0 Data Pin (SDO5_1/SDI0_1) 9.2.7 Receiver Serial Clock (SCKR_1) 9.2.8 Transmitter Serial Clock (SCKT_1) 9.2.9 Frame Sync for Receiver (FSR_1) 9.2.10 Frame Sync for Transmitter (FST_1) 204 9.3 E SAI_1 Programming Model213 9.4 Operating Modes9.5 GPIO - Pins and Registers 217 10 Digital Audio Transmitter231 11 Timer/ Event Counter253 Appendix A Bootstrap ROM ContentsA.1 DSP56366 Bootstrap Program 267 Appendix B Equates301 Appendix C JTAG BSDL309 Appendix D Programmers Reference324 Central Processor* *Figure D-2. Operating Mode Register (OMR) 325 Central Processor327 CENTRAL PROCESSORFigure D-4. Interrupt Priority Register Peripherals (IPRP) Figure D-5. Phase Lock Loop Control Register (PCTL)D-20 Freescale Semiconductor Application: Date: Programmer: Sheet 5 of 5 Clock Output Disable (COD) 19 18 17 1623 22 21 20 1514131211109876543210 328 PLL0 = 50% Duty Cycle Clock 1 = Pin Held In High State Figure D-6. Host Receive and Host Transmit Data Registers 329 HOST (HDI08)DSP SideFigure D-7. Host Control and Status Registers 330 HOST(HDI08)7 8 Figure D-8. Host Base Address and Host Port ControlFreescale Semiconductor D-23 331 HOST (HDI08) Host Base Address Register (HBAR) X:$FFFFC5 Reset = $80 8 1514131211109876543210Host Chip Select Polarity 0 = HCS Active LowHost Dual Data Strobe 0 = Single Strobe, 1 = Dual Strobe Host Multiplexed Bus 0 = Nonmultiplexed, 1 = Multiplexed Host Address Strobe Polarity 0 = Strobe Active Low, 1 = Strobe Active High Host Data Strobe Polarity 0 = Strobe Active Low, 1 = Strobe Active High HTRQ & HRRQ Enable 1 = HCS Active High DSP SideFigure D-9. Host Interrupt Control and Interrupt StatusD-24 Freescale Semiconductor Sheet 4 of 6 765 4 3 21 0 332 HOST (HDI08)Processor Side HOST (HDI08) 333 Processor SideFigure D-11. Host Receive and Transmit Byte Registers 334 HOST (HDI08)Receive Byte Registers Transmit Byte Registers Processor Side 336 SHIFigure D-14. SHI Host Control/Status Register Sheet 3 of 3Freescale Semiconductor D-29 337 SHI *SHI Control/Status X:$FFFF91 Reset = $008200 Register (HCSR) Figure D-15. ESAI Transmit Clock Control RegisterApplication: Date: Programmer: 338 TCCR - ESAI Transmit Clock Control RegisterX: $FFFFB6 Reset: $000000 339 TCR - ESAI Transmit Control RegisterX: $FFFFB5 Reset: $000000Figure D-16. ESAI Transmit Control Register Application: D ate: *Figure D-17. ESAI Receive Clock Control Register 340 ESAIX: $FFFFB8 Reset: $000000 RCCR - ESAI Receive Clock Control RegisterFigure D-18. ESAI Receive Control RegisterFreescale Semiconductor D-33 341 ESAI356 GPIO
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