Texas Instruments TMS320C6202 manuals

Texas Instruments TMS320C6202 Specifications

74 pages1.01 Mb

2TMS320C6202
3TMS320C6202
- description
- device characteristics
- 4functional block diagram
- 5CPU description
6TMS320C6202
- CPU description (continued)
  - Figure 1. TMS320C62x CPU Block Diagram
- 7CPU description (continued)
  - Figure 2. TMS320C62x CPU Data Paths
- 8signal groups description
  - Figure 3. CPU Signals
- 9signal groups description (continued)
  - Figure 4. Peripheral Signals
- 10signal groups description (continued)
  - Figure 4. Peripheral Signals (Continued)
  - 11Signal Descriptions
    - clock PLL
    - 16do not
20TMS320C6202
- 22development support
  - TMS320 DSP Development Support Reference Guide
  - TMS320 Third-Party Support Reference Guide
    - 24device and development-support tool nomenclature (continued)
    - Figure 5. TMS320 Device Nomenclature (Including TMS320C6202)
- 25documentation support
  - TMS320C6000 CPU and Instruction Set Reference Guide
  - Code Composer Studio Tutorial
  - Code Composer Users Guide
  - TMS320C6000 DSP/BIOS Users Guide
  - TMS320C62x Multichannel Evaluation Module Technical Reference
  - TMS320C62x Multichannel Evaluation Module Users Guide
  - TMS320C6x Evaluation Module Reference Guide
  - TMS320C6000 Assembly Language T ools Users Guide
  - TMS320C6x Peripheral Support Library Programmers Reference
  - TMS320C6x C Source Debugger Users Guide
  - TMS320C6000 Programmers Guide
  - TMS320C6000 Peripherals Reference Guide
- 27clock PLL
  - input and output clocks
    - section for input clock timing requirements.
    - Figure 6. PLL Block Diagram T able 3. TMS320C6202 PLL Component Selection T able
- power-supply sequencing
- 28absolute maximum ratings over operating case temperature range (unless otherwise noted)
- recommended operating conditions
- 29PARAMETER MEASUREMENT INFORMATION
- signal transition levels
  - All input and output timing parameters are referenced to 1.5 V for both 0 and 1 logic levels.
  - Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements
- 30INPUT AND OUTPUT CLOCKS timing requirements for CLKIN (see Figure 8)
  - Figure 8. CLKIN Timings
- timing requirements for XCLKIN (see Figure 9)
  - Figure 9. XCLKIN Timings
- 31INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for CLKOUT1 (see Figure 10)
  - Figure 10. CLKOUT1 Timings
- switching characteristics for CLKOUT2 (see Figure 11)
  - Figure 11. CLKOUT2 Timings
32TMS320C6202
- INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for XFCLK (see Figure 12)
  - Figure 12. XFCLK Timings
- 33switching characteristics for asynchronous memory cycles (see Figure 13 Figure 14)
- 34ASYNCHRONOUS MEMORY TIMING (CONTINUED)
  - Figure 13. Asynchronous Memory Read Timing
  - Figure 14. Asynchronous Memory Write Timing
- 35switching characteristics for synchronous-burst SRAM cycles (see Figure 15 and Figure 16)
- 36SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
  - Figure 15. SBSRAM Read Timing
  - Figure 16. SBSRAM Write Timing
- 37SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 17)
- switching characteristics for synchronous DRAM cycles (see Figure 17Figure 22)
  - 38Figure 17. Three SDRAM READ Commands
  - Figure 18. Three SDRAM WRT Commands
  - 39Figure 19. SDRAM ACTV Command
  - Figure 20. SDRAM DCAB Command
  - 40Figure 21. SDRAM REFR Command
  - Figure 22. SDRAM MRS Command
- 41HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles (see Figure 23)
- switching characteristics for the HOLD/HOLDA cycles (see Figure 23)
  - Figure 23. HOLD/HOLDA Timing
- 42RESET TIMING timing requirements for reset (see Figure 24)
  - clock PLL
- switching characteristics during reset (see Figure 24)
- 43RESET TIMING (CONTINUED)
  - Figure 24. Reset Timing
- 44EXTERNAL INTERRUPT TIMING timing requirements for interrupt response cycles (see Figure 25)
- switching characteristics during interrupt response cycles (see Figure 25)
  - Figure 25. Interrupt Timing
- 45switching characteristics for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28)
  - Figure 26. FIFO Read Timing (Glueless Read Mode)
- 46EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)
  - Figure 27. FIFO Read Timing
  - Figure 28. FIFO Write Timing
- 47switching characteristics for asynchronous peripheral cycles (see Figure 29Figure 30)
- 48EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)
  - Figure 29. Expansion Bus Asynchronous Peripheral Read Timing
  - Figure 30. Expansion Bus Asynchronous Peripheral Write Timing
- 49switching characteristics with external device as bus master (see Figure 31 and Figure 32)
  - 50Figure 31. External Host as Bus MasterRead
  - 51Figure 32. External Host as Bus MasterWrite
- 52timing requirements with C6202 as bus master (see Figure 33, Figure 34, and Figure 35)
- switching characteristics with C6202 as bus master (see Figure 33, Figure 34, and Figure 35)
  - 53Figure 33. C6202 as Bus MasterRead
  - Figure 34. C6202 as Bus MasterWrite
  - 54Figure 35. C6202 as Bus MasterBOFF Operation
- 55Figure 36. External Device as Asynchronous MasterRead
- 56EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING (CONTINUED)
  - Figure 37. External Device as Asynchronous MasterWrite
- 57switching characteristics for expansion bus arbitration (internal arbiter enabled) (see Figure 38)
  - Figure 38. Expansion Bus ArbitrationInternal Arbiter Enabled
- 58Figure 39. Expansion Bus ArbitrationInternal Arbiter Disabled
- 59MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP (see Figure 40)
- 60switching characteristics for McBSP (see Figure 40)
  - 61Figure 40. McBSP Timings
62TMS320C6202
- timing requirements for FSR when GSYNC = 1 (see Figure 41)
  - Figure 41. FSR Timing When GSYNC = 1
- 63timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 42)
- switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 42)
- 65timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 43)
- Figure 43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
- 66timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 44)
- switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 44)
- 68timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 45)
- Figure 45. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
- 69DMAC, TIMER, POWER-DOWN TIMING switching characteristics for DMAC outputs (see Figure 46)
  - Figure 46. DMAC Timing
- timing requirements for timer inputs (see Figure 47)
- switching characteristics for timer outputs (see Figure 47)
  - Figure 47. Timer Timing
- 71JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 49)
- switching characteristics for JTAG test port (see Figure 49)
  - Figure 49. JTAG Test-Port Timing
- 72MECHANICAL DATA
  - GJL (S-PBGA-N352) PLASTIC BALL GRID ARRAY
- thermal resistance characteristics (S-PBGA package)
- 73MECHANICAL DATA
  - GLS (S-PBGA-N384) PLASTIC BALL GRID ARRAY
- thermal resistance characteristics (S-PBGA package)