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Texas Instruments TMS320C6202 Input and Output Clocks, Timing requirements for CLKIN² see Figure

Models: TMS320C6202

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ADVANCE INFORMATION

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

INPUT AND OUTPUT CLOCKS

timing requirements for CLKIN² (see Figure 8)

				'C6202-200		'C6202-233		'C6202-250

	NO.			CLKMODE	CLKMODE	CLKMODE	CLKMODE	CLKMODE	CLKMODE	UNIT
	NO.			= x4	= x1	= x4	= x1	= x4	= x1	UNIT
				= x4	= x1	= x4	= x1	= x4	= x1

				MIN MAX	MIN MAX	MIN MAX	MIN MAX	MIN MAX	MIN MAX

	1	tc(CLKIN)	Cycle time,	20	5	17.2	4.3	16	4	ns
	1	tc(CLKIN)	CLKIN	20	5	17.2	4.3	16	4	ns
			CLKIN

	2	tw(CLKINH)	Pulse duration,	8	2.25	6.9	1.9	6.4	1.8	ns
	2	tw(CLKINH)	CLKIN high	8	2.25	6.9	1.9	6.4	1.8	ns
			CLKIN high

	3	tw(CLKINL)	Pulse duration,	8	2.25	6.9	1.9	6.4	1.8	ns
	3	tw(CLKINL)	CLKIN low	8	2.25	6.9	1.9	6.4	1.8	ns
			CLKIN low

	4	tt(CLKIN)	Transition time,	5	0.6	5	0.6	5	0.6	ns
	4	tt(CLKIN)	CLKIN	5	0.6	5	0.6	5	0.6	ns
			CLKIN

²The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH.

1

CLKIN

2

4

3

Figure 8. CLKIN Timings

4

timing requirements for XCLKIN²³ (see Figure 9)

'C6202-200

NO.

'C6202-233

UNIT

'C6202-250

MIN

MAX

1

tc(XCLKIN)

Cycle time, XCLKIN

4P

ns

2

tw(XCLKINH)

Pulse duration, XCLKIN high

1.8P

ns

3

tw(XCLKINL)

Pulse duration, XCLKIN low

1.8P

ns

4

tt(XCLKIN)

Transition time, XCLKIN

0.6

ns

²The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. ³ P = 1/CPU clock frequency in nanoseconds (ns).

1

4

2

XCLKIN

3

4

Figure 9. XCLKIN Timings

30	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

Image 30

Texas Instruments TMS320C6202 Input and Output Clocks, Timing requirements for CLKIN² see Figure, Clkmode Unit MIN MAX

Contents

Advance Information FIXED-POINT Digital Signal Processor Device characteristics Characteristics DescriptionDescription CPU Functional block diagramTimers Data Memory Interrupt Selector EmifCPU description Control TimersBit Data C62x CPU RegistersLD1 RSV2 RSV1 RSV0 Signal groups descriptionEMU1 EMU0 RSV4 RSV3 Clock/PLL Ieee Standard 1149.1CE0 CE3 CE2CE1 BE3 Hold BE2XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2 Xrdy Xhold XholdaFIXED-POINT Digital Signal Processor TMS320C6202Signal PIN no TYPE² Description Name GJL GLS Expansion BUS Emif ± Address Signal PIN no TYPE² Description Name GJL GLS Emif ± Address Emif ± DataMultichannel Buffered Serial Port 0 McBSP0 TimersEmif ± BUS Arbitration Multichannel Buffered Serial Port 1 McBSP1Signal PIN no TYPE² Description Name GJL GLS Multichannel Buffered Serial Port 2 McBSP2Reserved for Test AE8 AD6AE7 CvddAC4 AB4AC3 AC5 CvddGround Pins VSSGND Signal PIN no TYPE² Description Name GJL GLS Ground Pins AF10 Development support Development Tool Platform Part NumberScsi TMDS00510WS TMS Device Family Temperature Range Default 0 C to 90 CPrefix Device Speed Range Package Type ²Documentation support Advance Information Power-supply sequencing Clock PLLRecommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit IOL Signal transition levelsParameter Measurement Information IOHTiming requirements for Xclkin ²³ see Figure Input and Output ClocksTiming requirements for CLKIN² see Figure Clkmode Unit MIN MAXParameter Switching characteristics for CLKOUT1²³ see FigureSwitching characteristics for CLKOUT2 ³ see Figure Clkmode =Switching characteristics for XFCLK²³ see Figure Xfclk TimingsAsynchronous Memory Timing AWESetup = Strobe = Not ready = Hold = CEx BE30 EA212 ED310AOE Are AWE Ardy SYNCHRONOUS-BURST Memory Timing Unit MIN MAXEA212 ED310 CEx BE30BE1 BE2 BE3 BE4 SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE²Synchronous Dram Timing Timing requirements for synchronous Dram cycles see FigureCA1 CA2 CA3 Read CLKOUT2BE1 BE2 BE3 SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE²Dcab ActvSDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE² SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²Refr CLKOUT2 MRSSDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ² Hold Holda HOLD/HOLDA TimingTiming requirements for HOLD/HOLDA cycles ² see Figure Emif Bus² DSP Owns BusSwitching characteristics during reset¶ see Figure Reset TimingTiming requirements for reset see Figure Reset CLKOUT1FIXED-POINT Digital Signal Processor External Interrupt Timing EXTINTx, NMI Intr FlagINUMx Parameter MIN MAX Unit Expansion BUS Synchronous Fifo TimingMIN MAX Unit XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT §XA2 XA3XA4 XA1XOE XRE XWE/XWAIT³ XA3 XA4 XOE XRE XWE/XWAIT ³Expansion BUS Asynchronous Peripheral Timing XCEx XBE30/XA52 ² XD310 XOE XRE XWE/XWAIT ³ Xrdy §XOE XRE XWE/XWAIT ³ XRDY§ Expansion BUS Synchronous Host Port Timing Xblast § Xclkin XCS XAS XcntlXW/R ² XBE30/XA52 ³ XRDY¶XBLAST§ Xclkin XCS XAS Xcntl XW/R²XBE30/XA52³ XBE1 XBE2 XBE3 XBE4TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5 Xclkin XAS Xblast ³Xrdy XWE/XWAIT ¶ XBE30/XA52 § Addr XD310 Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda #XBE30/XA52 ² XR/W ³ XD310 Word Expansion BUS Asynchronous Host Port TimingXCS Xcntl XrdyExternal Device as Asynchronous MasterÐWrite XBE30/XA52² XR/W ³ XD310 WordXHOLD/XHOLDA Timing DSP Owns Bus External Requestor Xhold inputXBus ² C6202 Expansion Bus ArbitrationÐInternal Arbiter Disabled Xhold output Xholda input XBus ² C6202Multichannel Buffered Serial Port Timing Timing requirements for McBSP²³ see FigureSwitching characteristics for McBSP²³ see Figure Bitn-1 Clks ClkrFSR int ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/Xneeds resync Master Slave MIN MAX Master § Slave MIN MAXClkx FSX Bit Bitn-1McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = MASTER§ Slave MIN MAX FIXED-POINT Digital Signal Processor McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs ² see Figure DMAC, TIMER, POWER-DOWN TimingSwitching characteristics for Dmac outputs² see Figure Switching characteristics for timer outputs² see FigureSwitching characteristics for power-down outputs² see Figure TwPDH Pulse duration, PD high 10PJtag TEST-PORT Timing Switching characteristics for Jtag test port see FigureDTCKL-TDOV Delay time, TCK low to TDO valid Timing requirements for Jtag test port see FigureThermal resistance characteristics S-PBGA package Mechanical Data80 MAX 18,10 16,80 TYP 17,90Heat Slug 4188959/B 12/98Important Notice