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Texas Instruments TMS320C6202 specifications Asynchronous Memory Timing, Awe

Models: TMS320C6202

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TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

ASYNCHRONOUS MEMORY TIMING

timing requirements for asynchronous memory cycles² (see Figure 13 ± Figure 14)

			'C6202-200
NO.			'C6202-233		UNIT
NO.			'C6202-250		UNIT
			'C6202-250

			MIN	MAX

6	tsu(EDV-CKO1H)	Setup time, read EDx valid before CLKOUT1 high	4.0		ns
7	th(CKO1H-EDV)	Hold time, read EDx valid after CLKOUT1 high	0		ns
10	tsu(ARDY-CKO1H)	Setup time, ARDY valid before CLKOUT1 high	4.0		ns
11	th(CKO1H-ARDY)	Hold time, ARDY valid after CLKOUT1 high	0		ns

²To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.

switching characteristics for asynchronous memory cycles³ (see Figure 13 ± Figure 14)

'C6202-200

NO.

PARAMETER

'C6202-233

UNIT

'C6202-250

MIN

MAX

1

td(CKO1H-CEV)

Delay time, CLKOUT1 high to

valid

0

4.0

ns

CEx

2

td(CKO1H-BEV)

Delay time, CLKOUT1 high to

valid

0

4.0

ns

BEx

3

td(CKO1H-BEIV)

Delay time, CLKOUT1 high to

invalid

0

4.0

ns

BEx

4

td(CKO1H-EAV)

Delay time, CLKOUT1 high to EAx valid

0

4.0

ns

5

td(CKO1H-EAIV)

Delay time, CLKOUT1 high to EAx invalid

0

4.0

ns

8

td(CKO1H-AOEV)

Delay time, CLKOUT1 high to

valid

0

4.0

ns

AOE

9

td(CKO1H-AREV)

Delay time, CLKOUT1 high to

valid

0

4.0

ns

ARE

12

td(CKO1H-EDV)

Delay time, CLKOUT1 high to EDx valid

4.0

ns

13

td(CKO1H-EDIV)

Delay time, CLKOUT1 high to EDx invalid

0

ns

14

td(CKO1H-AWEV)

Delay time, CLKOUT1 high to

valid

0

4.0

ns

AWE

³ The minimum delay is also the minimum output hold after CLKOUT1 high.

ADVANCE INFORMATION

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

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Image 33

Texas Instruments TMS320C6202 specifications Asynchronous Memory Timing, Awe

Contents

Advance Information FIXED-POINT Digital Signal Processor Device characteristics Characteristics DescriptionDescription Timers Data Memory Interrupt Selector Functional block diagramCPU EmifCPU description Bit Data C62x CPU TimersControl RegistersLD1 EMU1 EMU0 RSV4 RSV3 Signal groups descriptionRSV2 RSV1 RSV0 Clock/PLL Ieee Standard 1149.1CE1 CE3 CE2CE0 BE3 Hold BE2Xrdy Xhold Xholda XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2TMS320C6202 FIXED-POINT Digital Signal ProcessorSignal PIN no TYPE² Description Name GJL GLS Expansion BUS Emif ± Address Emif ± Data Signal PIN no TYPE² Description Name GJL GLS Emif ± AddressEmif ± BUS Arbitration TimersMultichannel Buffered Serial Port 0 McBSP0 Multichannel Buffered Serial Port 1 McBSP1Signal PIN no TYPE² Description Name GJL GLS Multichannel Buffered Serial Port 2 McBSP2Reserved for Test AE7 AD6AE8 CvddAC3 AB4AC4 AC5 CvddGround Pins VSSGND Signal PIN no TYPE² Description Name GJL GLS Ground Pins AF10 Development support Development Tool Platform Part NumberScsi TMDS00510WS TMS Prefix Device Speed Range Temperature Range Default 0 C to 90 CDevice Family Package Type ²Documentation support Advance Information Clock PLL Power-supply sequencingRecommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Parameter Measurement Information Signal transition levelsIOL IOHTiming requirements for CLKIN² see Figure Input and Output ClocksTiming requirements for Xclkin ²³ see Figure Clkmode Unit MIN MAXSwitching characteristics for CLKOUT2 ³ see Figure Switching characteristics for CLKOUT1²³ see FigureParameter Clkmode =Xfclk Timings Switching characteristics for XFCLK²³ see FigureAWE Asynchronous Memory TimingSetup = Strobe = Not ready = Hold = CEx BE30 EA212 ED310AOE Are AWE Ardy Unit MIN MAX SYNCHRONOUS-BURST Memory TimingBE1 BE2 BE3 BE4 CEx BE30EA212 ED310 SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE²Timing requirements for synchronous Dram cycles see Figure Synchronous Dram TimingBE1 BE2 BE3 Read CLKOUT2CA1 CA2 CA3 SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE²SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE² ActvDcab SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²Refr CLKOUT2 MRSSDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ² Timing requirements for HOLD/HOLDA cycles ² see Figure HOLD/HOLDA TimingHold Holda Emif Bus² DSP Owns BusTiming requirements for reset see Figure Reset TimingSwitching characteristics during reset¶ see Figure Reset CLKOUT1FIXED-POINT Digital Signal Processor External Interrupt Timing EXTINTx, NMI Intr FlagINUMx MIN MAX Unit Expansion BUS Synchronous Fifo TimingParameter MIN MAX Unit XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT §XOE XRE XWE/XWAIT³ XA1XA2 XA3XA4 XA3 XA4 XOE XRE XWE/XWAIT ³Expansion BUS Asynchronous Peripheral Timing XCEx XBE30/XA52 ² XD310 XOE XRE XWE/XWAIT ³ Xrdy §XOE XRE XWE/XWAIT ³ XRDY§ Expansion BUS Synchronous Host Port Timing XW/R ² XBE30/XA52 ³ Xclkin XCS XAS XcntlXblast § XRDY¶XBE30/XA52³ Xclkin XCS XAS Xcntl XW/R²XBLAST§ XBE1 XBE2 XBE3 XBE4TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5 Xclkin XAS Xblast ³Xrdy XWE/XWAIT ¶ Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda # XBE30/XA52 § Addr XD310XCS Xcntl Expansion BUS Asynchronous Host Port TimingXBE30/XA52 ² XR/W ³ XD310 Word XrdyXBE30/XA52² XR/W ³ XD310 Word External Device as Asynchronous MasterÐWriteXHOLD/XHOLDA Timing DSP Owns Bus External Requestor Xhold inputXBus ² C6202 Xhold output Xholda input XBus ² C6202 Expansion Bus ArbitrationÐInternal Arbiter DisabledTiming requirements for McBSP²³ see Figure Multichannel Buffered Serial Port TimingSwitching characteristics for McBSP²³ see Figure FSR int Clks ClkrBitn-1 ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/Xneeds resync Master § Slave MIN MAX Master Slave MIN MAXBit Bitn-1 Clkx FSXMcBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = MASTER§ Slave MIN MAX FIXED-POINT Digital Signal Processor McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Switching characteristics for Dmac outputs² see Figure DMAC, TIMER, POWER-DOWN TimingTiming requirements for timer inputs ² see Figure Switching characteristics for timer outputs² see FigureTwPDH Pulse duration, PD high 10P Switching characteristics for power-down outputs² see FigureDTCKL-TDOV Delay time, TCK low to TDO valid Switching characteristics for Jtag test port see FigureJtag TEST-PORT Timing Timing requirements for Jtag test port see FigureMechanical Data Thermal resistance characteristics S-PBGA packageHeat Slug 18,10 16,80 TYP 17,9080 MAX 4188959/B 12/98Important Notice