TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING

timing requirements with external device as asynchronous bus master² (see Figure 36 and Figure 37)

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MIN

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

tw(XCSL)

Pulse duration,

 

 

 

low

 

 

 

 

 

 

 

 

4P

ns

XCS

 

 

 

 

 

 

 

 

 

2

tw(XCSH)

Pulse duration,

 

 

 

high

 

 

 

 

 

 

 

 

4P

ns

XCS

 

 

 

 

 

 

 

 

3

t

Setup time, expansion bus select signals³

 

valid before

 

 

low

2

 

ns

 

XCS

 

 

su(XSEL-XCSL)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

t

Hold time, expansion bus select signals³

valid after

 

 

low

2

 

ns

XCS

 

 

h(XCSL-XSEL)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

th(XRYL-XCSL)

Hold time,

 

 

low after XRDY low

 

 

 

 

 

 

 

 

P

ns

XCS

 

 

 

 

 

 

 

 

11

t

Setup time,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

ns

XBE[3:0]/XA[5:2] valid before XCS high§

 

 

su(XBEV-XCSH)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

th(XCSH-XBEV)

Hold time,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

ns

XBE[3:0]/XA[5:2] valid after XCS high§

 

13

tsu(XDV-XCSH)

Setup time, XDx valid before

 

 

high

 

 

 

 

 

 

 

 

2

 

ns

XCS

 

 

 

 

 

 

 

 

 

14

th(XCSH-XDV)

Hold time, XDx valid after

 

 

high

 

 

 

 

 

 

 

 

2

 

ns

XCS

 

 

 

 

 

 

 

 

 

²P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ³ Expansion bus select signals include XCNTL and XR/W.

§ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

switching characteristics with external device as asynchronous bus master (see Figure 36 and Figure 37)

NO.

 

 

 

PARAMETER

 

 

 

 

MIN

MAX

UNIT

5

td(XCSL-XDLZ)

Delay time, XCS low to XDx low impedance

 

 

 

0

 

ns

6

td(XCSH-XDIV)

Delay time, XCS high to XDx invalid

 

 

 

 

0

12

ns

7

td(XCSH-XDHZ)

Delay time, XCS high to XDx high impedance

 

 

 

 

12

ns

8

td(XRYL-XDV)

Delay time, XRDY low to XDx valid

 

 

 

 

0

4

ns

9

td(XCSH-XRYH)

Delay time, XCS high to XRDY high

 

 

 

 

0

12

ns

 

 

 

 

1

2

 

 

1

 

 

 

 

 

 

 

10

 

 

10

 

 

 

 

XCS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

4

 

 

3

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XCNTL

 

 

 

 

 

 

 

 

 

 

XBE[3:0]/XA[5:2]²

 

 

 

 

 

 

 

 

 

 

 

 

3

4

 

 

3

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XR/W³

 

 

 

 

 

 

 

 

 

 

 

 

3

4

 

 

3

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XR/W³

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

 

7

 

 

 

 

 

5

8

6

 

5

8

6

 

 

 

XD[31:0]

 

 

Word

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

9

 

 

 

XRDY

 

 

 

 

 

 

 

 

 

 

²XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses. ³ XW/R input/output polarity selected at boot

Figure 36. External Device as Asynchronous MasterÐRead

ADVANCE INFORMATION

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251±1443

55

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Texas Instruments TMS320C6202 Expansion BUS Asynchronous Host Port Timing, XCS Xcntl, XBE30/XA52 ² XR/W ³ XD310 Word, Xrdy

TMS320C6202 specifications

The Texas Instruments TMS320C6202 is a powerful digital signal processor (DSP) that is well-regarded in the realm of high-performance computing applications. As part of the TMS320C6000 family, the C6202 was designed to meet the demanding requirements of telecommunications, audio and video processing, and other real-time digital signal processing tasks.

One of the primary features of the TMS320C6202 is its superscalar architecture. This allows the processor to execute multiple instructions simultaneously, significantly improving throughput and efficiency. With two functional units, the DSP can execute both fixed-point and floating-point operations in parallel, optimizing performance for various computational workloads.

The core clock frequency of the TMS320C6202 typically reaches up to 150 MHz, which means it can process instructions at impressive speeds. This high frequency, combined with an advanced instruction set that includes efficient looping and branching instructions, makes the C6202 highly adept at handling complex algorithms common in digital signal processing.

Memory access is another critical characteristic of the TMS320C6202. It supports a unified memory architecture featuring both on-chip SRAM and external memory interfaces. This enables seamless data transfer between the processor and memory, improving overall system performance. The processor can interface with diverse memory types, including SDRAM and other high-speed memory technologies, further enhancing its versatility.

Furthermore, the TMS320C6202 incorporates a range of built-in features designed to facilitate efficient development. Its integrated hardware multipliers and accumulators allow rapid computation of mathematical functions, while on-chip debugging support simplifies the development process. Additionally, the processor features a host of peripheral interfaces, enabling integrations for input/output operations, essential for real-time applications such as multimedia processing.

Texas Instruments excels in providing software and development tools for the TMS320C6202. The Code Composer Studio (CCS) and various libraries enhance the ease of programming and optimization for this DSP, which helps engineers accelerate product development.

Overall, the Texas Instruments TMS320C6202 is a robust digital signal processor characterized by its high-speed performance, dual functional units, innovative memory architecture, and support for sophisticated algorithms. It has become a preferred choice for applications requiring intensive signal processing capabilities, making significant contributions to fields such as telecommunications, multimedia, and industrial automation.