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Texas Instruments TMS320C6202 XHOLD/XHOLDA Timing, DSP Owns Bus External Requestor Xhold input

Models: TMS320C6202

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TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

XHOLD/XHOLDA TIMING

timing requirements for expansion bus arbitration (internal arbiter enabled)² (see Figure 38)

NO.		MIN	MAX	UNIT

3	toh(XHDAH-XHDH)Output hold time, XHOLD high after XHOLDA high	P		ns

² P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

switching characteristics for expansion bus arbitration (internal arbiter enabled)²³ (see Figure 38)

NO.		PARAMETER	MIN	MAX	UNIT

1	tR(XHDH-XBHZ)	Response time, XHOLD high to XBus high impedance	4P	§	ns
2	td(XBHZ-XHDAH)	Delay time, XBus high impedance to XHOLDA high	0	2P	ns
4	tR(XHDL-XHDAL)	Response time, XHOLD low to XHOLDA low	4P		ns
5	td(XHDAL-XBLZ)	Delay time, XHOLDA low to XBus low impedance	0	2P	ns

²P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ³ XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.

§ All pending XBus transactions are allowed to complete before XHOLDA is asserted.

	DSP Owns Bus	External Requestor	DSP Owns Bus
	DSP Owns Bus	Owns Bus	DSP Owns Bus
		Owns Bus	3
			3
XHOLD (input)
		2	4
XHOLDA (output)
		1	5
XBus²	C6202		C6202

² XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.

Figure 38. Expansion Bus ArbitrationÐInternal Arbiter Enabled

ADVANCE INFORMATION

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

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Texas Instruments TMS320C6202 specifications XHOLD/XHOLDA Timing, DSP Owns Bus External Requestor Xhold input, XBus ² C6202

Contents

Advance Information FIXED-POINT Digital Signal Processor Device characteristics Characteristics DescriptionDescription Timers Data Memory Interrupt Selector Functional block diagramCPU EmifCPU description Bit Data C62x CPU TimersControl RegistersLD1 EMU1 EMU0 RSV4 RSV3 Signal groups descriptionRSV2 RSV1 RSV0 Clock/PLL Ieee Standard 1149.1CE1 CE3 CE2CE0 BE3 Hold BE2Xrdy Xhold Xholda XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2TMS320C6202 FIXED-POINT Digital Signal ProcessorSignal PIN no TYPE² Description Name GJL GLS Expansion BUS Emif ± Address Emif ± Data Signal PIN no TYPE² Description Name GJL GLS Emif ± AddressEmif ± BUS Arbitration TimersMultichannel Buffered Serial Port 0 McBSP0 Multichannel Buffered Serial Port 1 McBSP1Signal PIN no TYPE² Description Name GJL GLS Multichannel Buffered Serial Port 2 McBSP2Reserved for Test AE7 AD6AE8 CvddAC3 AB4AC4 AC5 CvddGround Pins VSSGND Signal PIN no TYPE² Description Name GJL GLS Ground Pins AF10 Development support Development Tool Platform Part NumberScsi TMDS00510WS TMS Prefix Device Speed Range Temperature Range Default 0 C to 90 CDevice Family Package Type ²Documentation support Advance Information Clock PLL Power-supply sequencingRecommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Parameter Measurement Information Signal transition levelsIOL IOHTiming requirements for CLKIN² see Figure Input and Output ClocksTiming requirements for Xclkin ²³ see Figure Clkmode Unit MIN MAXSwitching characteristics for CLKOUT2 ³ see Figure Switching characteristics for CLKOUT1²³ see FigureParameter Clkmode =Xfclk Timings Switching characteristics for XFCLK²³ see FigureAWE Asynchronous Memory TimingSetup = Strobe = Not ready = Hold = CEx BE30 EA212 ED310AOE Are AWE Ardy Unit MIN MAX SYNCHRONOUS-BURST Memory TimingBE1 BE2 BE3 BE4 CEx BE30EA212 ED310 SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE²Timing requirements for synchronous Dram cycles see Figure Synchronous Dram TimingBE1 BE2 BE3 Read CLKOUT2CA1 CA2 CA3 SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE²SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE² ActvDcab SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²Refr CLKOUT2 MRSSDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ² Timing requirements for HOLD/HOLDA cycles ² see Figure HOLD/HOLDA TimingHold Holda Emif Bus² DSP Owns BusTiming requirements for reset see Figure Reset TimingSwitching characteristics during reset¶ see Figure Reset CLKOUT1FIXED-POINT Digital Signal Processor External Interrupt Timing EXTINTx, NMI Intr FlagINUMx MIN MAX Unit Expansion BUS Synchronous Fifo TimingParameter MIN MAX Unit XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT §XOE XRE XWE/XWAIT³ XA1XA2 XA3XA4 XA3 XA4 XOE XRE XWE/XWAIT ³Expansion BUS Asynchronous Peripheral Timing XCEx XBE30/XA52 ² XD310 XOE XRE XWE/XWAIT ³ Xrdy §XOE XRE XWE/XWAIT ³ XRDY§ Expansion BUS Synchronous Host Port Timing XW/R ² XBE30/XA52 ³ Xclkin XCS XAS XcntlXblast § XRDY¶XBE30/XA52³ Xclkin XCS XAS Xcntl XW/R²XBLAST§ XBE1 XBE2 XBE3 XBE4TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5 Xclkin XAS Xblast ³Xrdy XWE/XWAIT ¶ Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda # XBE30/XA52 § Addr XD310XCS Xcntl Expansion BUS Asynchronous Host Port TimingXBE30/XA52 ² XR/W ³ XD310 Word XrdyXBE30/XA52² XR/W ³ XD310 Word External Device as Asynchronous MasterÐWriteXHOLD/XHOLDA Timing DSP Owns Bus External Requestor Xhold inputXBus ² C6202 Xhold output Xholda input XBus ² C6202 Expansion Bus ArbitrationÐInternal Arbiter DisabledTiming requirements for McBSP²³ see Figure Multichannel Buffered Serial Port TimingSwitching characteristics for McBSP²³ see Figure FSR int Clks ClkrBitn-1 ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/Xneeds resync Master § Slave MIN MAX Master Slave MIN MAXBit Bitn-1 Clkx FSXMcBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = MASTER§ Slave MIN MAX FIXED-POINT Digital Signal Processor McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Switching characteristics for Dmac outputs² see Figure DMAC, TIMER, POWER-DOWN TimingTiming requirements for timer inputs ² see Figure Switching characteristics for timer outputs² see FigureTwPDH Pulse duration, PD high 10P Switching characteristics for power-down outputs² see FigureDTCKL-TDOV Delay time, TCK low to TDO valid Switching characteristics for Jtag test port see FigureJtag TEST-PORT Timing Timing requirements for Jtag test port see FigureMechanical Data Thermal resistance characteristics S-PBGA packageHeat Slug 18,10 16,80 TYP 17,9080 MAX 4188959/B 12/98Important Notice