ADVANCE INFORMATION

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

 

 

 

 

 

 

Signal Descriptions (Continued)

 

SIGNAL

PIN NO.

TYPE²

DESCRIPTION

 

NAME

GJL

GLS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXPANSION BUS

 

 

 

 

 

 

 

 

XCLKIN

A9

C8

I

Expansion bus synchronous host interface clock input

 

 

 

 

 

 

 

 

XFCLK

B9

A8

O

Expansion bus FIFO interface clock output

 

 

 

 

 

 

 

 

XD31

D15

C13

 

 

 

 

 

 

 

 

 

 

XD30

B16

A13

 

 

 

 

 

 

 

 

 

 

XD29

A17

C14

 

 

 

 

 

 

 

 

 

 

XD28

B17

B14

 

 

 

 

 

 

 

 

 

 

XD27

D16

B15

 

 

 

 

 

 

 

 

 

 

XD26

A18

C15

 

 

 

 

 

 

 

 

 

 

XD25

B18

A15

 

 

 

 

 

 

 

 

 

 

XD24

D17

B16

 

 

 

 

 

 

 

 

 

 

XD23

C18

C16

 

 

 

 

 

 

 

 

 

 

XD22

A20

A17

 

 

 

 

 

 

 

 

 

 

XD21

D18

B17

 

 

 

 

 

 

 

 

 

 

XD20

C19

C17

 

Expansion bus data

 

 

 

 

 

 

 

XD19

A21

B18

 

 

 

Used for transfer of data, address, and control

 

XD18

D19

A19

 

Also controls initialization of DSP modes and expansion bus at reset via pullup/pulldown

 

 

 

 

 

 

resistors

 

XD17

C20

C18

 

 

 

± XCE[3:0] memory type

 

 

 

 

 

 

 

XD16

B21

B19

 

 

I/O/Z

± XBLAST polarity

 

XD15

A22

C19

± XW/R polarity

 

 

 

 

 

 

 

 

± Asynchronous or synchronous host operation

 

XD14

D20

B20

 

 

 

± Arbitration mode (internal or external)

 

 

 

 

 

 

 

XD13

B22

A21

 

 

 

± FIFO mode

 

XD12

E25

C21

 

± Little endian/big endian

 

 

 

 

 

 

± Boot mode

 

XD11

F24

D20

 

 

 

 

 

 

 

 

 

 

 

 

XD10

E26

B22

 

 

 

 

 

 

 

 

 

 

XD9

F25

D21

 

 

 

 

 

 

 

 

 

 

XD8

G24

E20

 

 

 

 

 

 

 

 

 

 

XD7

H23

E21

 

 

 

 

 

 

 

 

 

 

XD6

F26

D22

 

 

 

 

 

 

 

 

 

 

XD5

G25

F20

 

 

 

 

 

 

 

 

 

 

XD4

J23

F21

 

 

 

 

 

 

 

 

 

 

XD3

G26

E22

 

 

 

 

 

 

 

 

 

 

XD2

H25

G20

 

 

 

 

 

 

 

 

 

 

XD1

J24

G21

 

 

 

 

 

 

 

 

 

 

XD0

K23

G22

 

 

 

 

 

 

 

 

 

 

 

F2

D2

 

 

 

XCE3

 

 

 

 

 

 

 

 

 

Expansion bus I/O port memory space enables

 

 

 

 

 

 

 

XCE2

E1

B1

 

 

O/Z

Enabled by bits 28, 29, and 30 of the word address

 

 

 

 

 

 

 

 

 

 

 

XCE1

F3

D3

 

 

Only one asserted during any I/O port data access

 

 

 

 

 

 

 

 

 

E2

C2

 

 

 

XCE0

 

 

 

² I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

12

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Page 12
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Texas Instruments TMS320C6202 specifications Signal PIN no TYPE² Description Name GJL GLS Expansion BUS

TMS320C6202 specifications

The Texas Instruments TMS320C6202 is a powerful digital signal processor (DSP) that is well-regarded in the realm of high-performance computing applications. As part of the TMS320C6000 family, the C6202 was designed to meet the demanding requirements of telecommunications, audio and video processing, and other real-time digital signal processing tasks.

One of the primary features of the TMS320C6202 is its superscalar architecture. This allows the processor to execute multiple instructions simultaneously, significantly improving throughput and efficiency. With two functional units, the DSP can execute both fixed-point and floating-point operations in parallel, optimizing performance for various computational workloads.

The core clock frequency of the TMS320C6202 typically reaches up to 150 MHz, which means it can process instructions at impressive speeds. This high frequency, combined with an advanced instruction set that includes efficient looping and branching instructions, makes the C6202 highly adept at handling complex algorithms common in digital signal processing.

Memory access is another critical characteristic of the TMS320C6202. It supports a unified memory architecture featuring both on-chip SRAM and external memory interfaces. This enables seamless data transfer between the processor and memory, improving overall system performance. The processor can interface with diverse memory types, including SDRAM and other high-speed memory technologies, further enhancing its versatility.

Furthermore, the TMS320C6202 incorporates a range of built-in features designed to facilitate efficient development. Its integrated hardware multipliers and accumulators allow rapid computation of mathematical functions, while on-chip debugging support simplifies the development process. Additionally, the processor features a host of peripheral interfaces, enabling integrations for input/output operations, essential for real-time applications such as multimedia processing.

Texas Instruments excels in providing software and development tools for the TMS320C6202. The Code Composer Studio (CCS) and various libraries enhance the ease of programming and optimization for this DSP, which helps engineers accelerate product development.

Overall, the Texas Instruments TMS320C6202 is a robust digital signal processor characterized by its high-speed performance, dual functional units, innovative memory architecture, and support for sophisticated algorithms. It has become a preferred choice for applications requiring intensive signal processing capabilities, making significant contributions to fields such as telecommunications, multimedia, and industrial automation.