Texas Instruments TMS320C6202 specifications Emif ± Address

Models: TMS320C6202

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TMS320C6202

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIXED-POINT DIGITAL SIGNAL PROCESSOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signal Descriptions (Continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SIGNAL

PIN NO.

 

TYPE²

DESCRIPTION

 

 

NAME

GJL

GLS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXPANSION BUS (CONTINUED)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XBE3/XA5

C7

C5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Expansion bus multiplexed byte-enable control/address signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XBE2/XA4

D8

A4

 

 

 

 

I/O/Z

Act as byte enable for host port operation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XBE1/XA3

A6

B5

 

 

 

 

Act as address for I/O port operation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C8

C6

 

 

 

 

 

XBE0/XA2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A7

A6

 

O/Z

Expansion bus I/O port output enable

 

 

XOE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C9

C7

 

O/Z

Expansion bus I/O port read enable

 

 

XRE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D10

B7

 

O/Z

Expansion bus I/O port write enable and host port wait signals

 

 

XWE/XWAIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A10

C9

 

I

Expansion bus host port chip-select input

 

 

XCS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D9

B6

 

I/O/Z

Expansion bus host port address strobe

 

 

XAS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XCNTL

B10

B9

 

I

Expansion bus host control. XCNTL selects between expansion bus address or data register

 

 

 

 

 

 

 

 

 

 

 

 

 

XW/R

D11

B8

 

I/O/Z

Expansion bus host port write/read enable. XW/R polarity selected at reset

 

 

 

 

 

 

 

 

 

 

 

 

 

XRDY

A5

C4

 

I/O/Z

Expansion bus host port ready (active low) and I/O port ready (active high)

 

 

 

 

 

 

 

 

 

 

 

 

 

XBLAST

B6

B4

 

I/O/Z

Expansion bus host port burst last±polarity selected at reset

 

 

 

 

 

 

 

 

 

 

 

 

 

XBOFF

B11

A10

 

I

Expansion bus back off

 

 

 

 

 

 

 

 

 

 

 

 

 

XHOLD

B5

A2

 

I/O/Z

Expansion bus hold request

 

 

 

 

 

 

 

 

 

 

 

 

 

XHOLDA

D7

B3

 

I/O/Z

Expansion bus hold acknowledge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EMIF ± CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

 

 

 

 

 

 

 

 

 

 

 

 

CE3

 

AB25

Y21

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory space enables

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE2

AA24

W20

 

 

 

 

O/Z

Enabled by bits 24 and 25 of the word address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE1

AB26

AA22

 

 

Only one asserted during any external data access

 

 

 

 

 

 

 

 

 

 

 

AA25

W21

 

 

 

 

 

CE0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Y24

V20

 

 

 

 

 

BE3

 

 

 

Byte-enable control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W23

V21

 

 

 

BE2

 

 

O/Z

Decoded from the two lowest bits of the internal address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte-write enables for most types of memory

 

 

BE1

AA26

W22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Can be directly connected to SDRAM read and write mask signal (SDQM)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BE0

Y25

U20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EMIF ± ADDRESS

 

 

 

 

 

 

 

 

 

 

EA21

J25

H20

 

 

 

 

 

 

 

 

 

 

 

 

 

EA20

J26

H21

 

 

 

 

 

 

 

 

 

 

 

 

 

EA19

L23

H22

 

 

 

 

 

 

 

 

 

 

 

 

 

EA18

K25

J20

 

 

 

 

 

 

 

 

 

 

 

 

 

EA17

L24

J21

 

 

 

 

 

 

 

 

 

O/Z

External address (word address)

 

 

EA16

L25

K21

 

 

 

 

 

 

 

 

 

 

 

EA15

M23

K20

 

 

 

 

 

 

 

 

 

 

 

 

 

EA14

M24

K22

 

 

 

 

 

 

 

 

 

 

 

 

 

EA13

M25

L21

 

 

 

 

 

 

 

 

 

 

 

 

 

EA12

N23

L20

 

 

 

 

 

 

 

 

 

 

 

 

 

EA11

P24

L22

 

 

 

 

²I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

ADVANCE INFORMATION

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Texas Instruments TMS320C6202 specifications Emif ± Address

TMS320C6202 specifications

The Texas Instruments TMS320C6202 is a powerful digital signal processor (DSP) that is well-regarded in the realm of high-performance computing applications. As part of the TMS320C6000 family, the C6202 was designed to meet the demanding requirements of telecommunications, audio and video processing, and other real-time digital signal processing tasks.

One of the primary features of the TMS320C6202 is its superscalar architecture. This allows the processor to execute multiple instructions simultaneously, significantly improving throughput and efficiency. With two functional units, the DSP can execute both fixed-point and floating-point operations in parallel, optimizing performance for various computational workloads.

The core clock frequency of the TMS320C6202 typically reaches up to 150 MHz, which means it can process instructions at impressive speeds. This high frequency, combined with an advanced instruction set that includes efficient looping and branching instructions, makes the C6202 highly adept at handling complex algorithms common in digital signal processing.

Memory access is another critical characteristic of the TMS320C6202. It supports a unified memory architecture featuring both on-chip SRAM and external memory interfaces. This enables seamless data transfer between the processor and memory, improving overall system performance. The processor can interface with diverse memory types, including SDRAM and other high-speed memory technologies, further enhancing its versatility.

Furthermore, the TMS320C6202 incorporates a range of built-in features designed to facilitate efficient development. Its integrated hardware multipliers and accumulators allow rapid computation of mathematical functions, while on-chip debugging support simplifies the development process. Additionally, the processor features a host of peripheral interfaces, enabling integrations for input/output operations, essential for real-time applications such as multimedia processing.

Texas Instruments excels in providing software and development tools for the TMS320C6202. The Code Composer Studio (CCS) and various libraries enhance the ease of programming and optimization for this DSP, which helps engineers accelerate product development.

Overall, the Texas Instruments TMS320C6202 is a robust digital signal processor characterized by its high-speed performance, dual functional units, innovative memory architecture, and support for sophisticated algorithms. It has become a preferred choice for applications requiring intensive signal processing capabilities, making significant contributions to fields such as telecommunications, multimedia, and industrial automation.