Emif ± Address | Texas Instruments TMS320C6202 specs

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

Signal Descriptions (Continued)

SIGNAL

PIN NO.

TYPE²

DESCRIPTION

NAME

GJL

GLS

EXPANSION BUS (CONTINUED)

XBE3/XA5

C7

C5

Expansion bus multiplexed byte-enable control/address signals

XBE2/XA4

D8

A4

I/O/Z

• Act as byte enable for host port operation

XBE1/XA3

A6

B5

• Act as address for I/O port operation

C8

C6

XBE0/XA2

A7

A6

O/Z

Expansion bus I/O port output enable

XOE

C9

C7

O/Z

Expansion bus I/O port read enable

XRE

D10

B7

O/Z

Expansion bus I/O port write enable and host port wait signals

XWE/XWAIT

A10

C9

I

Expansion bus host port chip-select input

XCS

D9

B6

I/O/Z

Expansion bus host port address strobe

XAS

XCNTL

B10

B9

I

Expansion bus host control. XCNTL selects between expansion bus address or data register

XW/R

D11

B8

I/O/Z

Expansion bus host port write/read enable. XW/R polarity selected at reset

XRDY

A5

C4

I/O/Z

Expansion bus host port ready (active low) and I/O port ready (active high)

XBLAST

B6

B4

I/O/Z

Expansion bus host port burst last±polarity selected at reset

XBOFF

B11

A10

I

Expansion bus back off

XHOLD

B5

A2

I/O/Z

Expansion bus hold request

XHOLDA

D7

B3

I/O/Z

Expansion bus hold acknowledge

EMIF ± CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

CE3

AB25

Y21

Memory space enables

CE2

AA24

W20

O/Z

• Enabled by bits 24 and 25 of the word address

CE1

AB26

AA22

• Only one asserted during any external data access

AA25

W21

CE0

Y24

V20

BE3

Byte-enable control

W23

V21

BE2

O/Z

• Decoded from the two lowest bits of the internal address

• Byte-write enables for most types of memory

BE1

AA26

W22

• Can be directly connected to SDRAM read and write mask signal (SDQM)

BE0

Y25

U20

EMIF ± ADDRESS

EA21

J25

H20

EA20

J26

H21

EA19

L23

H22

EA18

K25

J20

EA17

L24

J21

O/Z

External address (word address)

EA16

L25

K21

EA15

M23

K20

EA14

M24

K22

EA13

M25

L21

EA12

N23

L20

EA11

P24

L22

²I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

ADVANCE INFORMATION

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

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Image 13

Texas Instruments TMS320C6202 specifications Emif ± Address

TMS320C6202 specifications

The Texas Instruments TMS320C6202 is a powerful digital signal processor (DSP) that is well-regarded in the realm of high-performance computing applications. As part of the TMS320C6000 family, the C6202 was designed to meet the demanding requirements of telecommunications, audio and video processing, and other real-time digital signal processing tasks.

One of the primary features of the TMS320C6202 is its superscalar architecture. This allows the processor to execute multiple instructions simultaneously, significantly improving throughput and efficiency. With two functional units, the DSP can execute both fixed-point and floating-point operations in parallel, optimizing performance for various computational workloads.

The core clock frequency of the TMS320C6202 typically reaches up to 150 MHz, which means it can process instructions at impressive speeds. This high frequency, combined with an advanced instruction set that includes efficient looping and branching instructions, makes the C6202 highly adept at handling complex algorithms common in digital signal processing.

Memory access is another critical characteristic of the TMS320C6202. It supports a unified memory architecture featuring both on-chip SRAM and external memory interfaces. This enables seamless data transfer between the processor and memory, improving overall system performance. The processor can interface with diverse memory types, including SDRAM and other high-speed memory technologies, further enhancing its versatility.

Furthermore, the TMS320C6202 incorporates a range of built-in features designed to facilitate efficient development. Its integrated hardware multipliers and accumulators allow rapid computation of mathematical functions, while on-chip debugging support simplifies the development process. Additionally, the processor features a host of peripheral interfaces, enabling integrations for input/output operations, essential for real-time applications such as multimedia processing.

Texas Instruments excels in providing software and development tools for the TMS320C6202. The Code Composer Studio (CCS) and various libraries enhance the ease of programming and optimization for this DSP, which helps engineers accelerate product development.

Overall, the Texas Instruments TMS320C6202 is a robust digital signal processor characterized by its high-speed performance, dual functional units, innovative memory architecture, and support for sophisticated algorithms. It has become a preferred choice for applications requiring intensive signal processing capabilities, making significant contributions to fields such as telecommunications, multimedia, and industrial automation.

Contents

Advance Information FIXED-POINT Digital Signal Processor Characteristics Description Device characteristicsDescription Timers Data Memory Interrupt Selector Functional block diagramCPU Emif CPU description Bit Data C62x CPU TimersControl Registers LD1 EMU1 EMU0 RSV4 RSV3 Signal groups descriptionRSV2 RSV1 RSV0 Clock/PLL Ieee Standard 1149.1 CE1 CE3 CE2CE0 BE3 Hold BE2 Xrdy Xhold Xholda XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2 TMS320C6202 FIXED-POINT Digital Signal Processor Signal PIN no TYPE² Description Name GJL GLS Expansion BUS Emif ± Address Emif ± Data Signal PIN no TYPE² Description Name GJL GLS Emif ± Address Emif ± BUS Arbitration TimersMultichannel Buffered Serial Port 0 McBSP0 Multichannel Buffered Serial Port 1 McBSP1 Multichannel Buffered Serial Port 2 McBSP2 Signal PIN no TYPE² Description Name GJL GLSReserved for Test AE7 AD6AE8 Cvdd AC3 AB4AC4 AC5 Cvdd VSS Ground PinsGND Signal PIN no TYPE² Description Name GJL GLS Ground Pins AF10 Development Tool Platform Part Number Development supportScsi TMDS00510WS TMS Prefix Device Speed Range Temperature Range Default 0 C to 90 CDevice Family Package Type ² Documentation support Advance Information Clock PLL Power-supply sequencing MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Parameter Measurement Information Signal transition levelsIOL IOH Timing requirements for CLKIN² see Figure Input and Output ClocksTiming requirements for Xclkin ²³ see Figure Clkmode Unit MIN MAX Switching characteristics for CLKOUT2 ³ see Figure Switching characteristics for CLKOUT1²³ see FigureParameter Clkmode = Xfclk Timings Switching characteristics for XFCLK²³ see Figure AWE Asynchronous Memory Timing CEx BE30 EA212 ED310 Setup = Strobe = Not ready = Hold =AOE Are AWE Ardy Unit MIN MAX SYNCHRONOUS-BURST Memory Timing BE1 BE2 BE3 BE4 CEx BE30EA212 ED310 SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE² Timing requirements for synchronous Dram cycles see Figure Synchronous Dram Timing BE1 BE2 BE3 Read CLKOUT2CA1 CA2 CA3 SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE² SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE² ActvDcab SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE² MRS Refr CLKOUT2SDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ² Timing requirements for HOLD/HOLDA cycles ² see Figure HOLD/HOLDA TimingHold Holda Emif Bus² DSP Owns Bus Timing requirements for reset see Figure Reset TimingSwitching characteristics during reset¶ see Figure Reset CLKOUT1 FIXED-POINT Digital Signal Processor EXTINTx, NMI Intr Flag External Interrupt TimingINUMx MIN MAX Unit Expansion BUS Synchronous Fifo TimingParameter MIN MAX Unit XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT § XOE XRE XWE/XWAIT³ XA1XA2 XA3XA4 XA3 XA4 XOE XRE XWE/XWAIT ³ Expansion BUS Asynchronous Peripheral Timing XOE XRE XWE/XWAIT ³ Xrdy § XCEx XBE30/XA52 ² XD310XOE XRE XWE/XWAIT ³ XRDY§ Expansion BUS Synchronous Host Port Timing XW/R ² XBE30/XA52 ³ Xclkin XCS XAS XcntlXblast § XRDY¶ XBE30/XA52³ Xclkin XCS XAS Xcntl XW/R²XBLAST§ XBE1 XBE2 XBE3 XBE4 TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5 Xblast ³ Xclkin XASXrdy XWE/XWAIT ¶ Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda # XBE30/XA52 § Addr XD310 XCS Xcntl Expansion BUS Asynchronous Host Port TimingXBE30/XA52 ² XR/W ³ XD310 Word Xrdy XBE30/XA52² XR/W ³ XD310 Word External Device as Asynchronous MasterÐWrite DSP Owns Bus External Requestor Xhold input XHOLD/XHOLDA TimingXBus ² C6202 Xhold output Xholda input XBus ² C6202 Expansion Bus ArbitrationÐInternal Arbiter Disabled Timing requirements for McBSP²³ see Figure Multichannel Buffered Serial Port Timing Switching characteristics for McBSP²³ see Figure FSR int Clks ClkrBitn-1 Clkx Clks Timing requirements for FSR when Gsync = 1 see FigureFSR external CLKR/X no need to resync CLKR/Xneeds resync Master § Slave MIN MAX Master Slave MIN MAX Bit Bitn-1 Clkx FSX McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = MASTER§ Slave MIN MAX FIXED-POINT Digital Signal Processor McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Switching characteristics for Dmac outputs² see Figure DMAC, TIMER, POWER-DOWN TimingTiming requirements for timer inputs ² see Figure Switching characteristics for timer outputs² see Figure TwPDH Pulse duration, PD high 10P Switching characteristics for power-down outputs² see Figure DTCKL-TDOV Delay time, TCK low to TDO valid Switching characteristics for Jtag test port see FigureJtag TEST-PORT Timing Timing requirements for Jtag test port see Figure Mechanical Data Thermal resistance characteristics S-PBGA package Heat Slug 18,10 16,80 TYP 17,9080 MAX 4188959/B 12/98 Important Notice