TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

EXPANSION BUS SYNCHRONOUS HOST PORT TIMING

timing requirements with external device as bus master (see Figure 31 and Figure 32)

NO.

 

 

 

 

 

 

 

 

 

 

 

MIN

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

tsu(XCSV-XCKIH)

Setup time,

 

 

 

 

valid before XCLKIN high

4

 

ns

XCS

 

2

th(XCKIH-XCS)

Hold time,

 

 

 

 

valid after XCLKIN high

2.3

 

ns

XCS

 

3

tsu(XAS-XCKIH)

Setup time,

 

 

 

 

valid before XCLKIN high

4

 

ns

XAS

 

4

th(XCKIH-XAS)

Hold time,

 

 

 

valid after XCLKIN high

2.3

 

ns

XAS

 

5

tsu(XCTL-XCKIH)

Setup time, XCNTL valid before XCLKIN high

4

 

ns

6

th(XCKIH-XCTL)

Hold time, XCNTL valid after XCLKIN high

2.3

 

ns

7

t

Setup time, XW/R valid before XCLKIN high²

4

 

ns

 

su(XWR-XCKIH)

 

 

 

 

 

 

 

 

 

 

 

 

 

8

t

Hold time, XW/R valid after XCLKIN high²

2.3

 

ns

 

h(XCKIH-XWR)

 

 

 

 

 

 

 

 

 

 

 

 

 

9

t

Setup time, XBLAST valid before XCLKIN high³

4

 

ns

 

su(XBLTV-XCKIH)

 

 

 

 

 

 

 

 

 

 

 

 

 

10

t

Hold time, XBLAST valid after XCLKIN high³

2.3

 

ns

 

h(XCKIH-XBLTV)

 

 

 

 

 

 

 

 

 

 

 

 

 

16

t

Setup time,

 

 

 

 

 

 

 

4

 

ns

XBE[3:0]/XA[5:2] valid before XCLKIN high§

 

 

su(XBEV-XCKIH)

 

 

 

 

 

 

 

 

 

 

 

 

 

17

t

Hold time,

 

 

2.3

 

ns

XBE[3:0]/XA[5:2] valid after XCLKIN high§

 

 

h(XCKIH-XBEV)

 

 

 

 

 

 

 

 

 

 

 

 

 

18

tsu(XD-XCKIH)

Setup time, XDx valid before XCLKIN high

4

 

ns

19

th(XCKIH-XD)

Hold time, XDx valid after XCLKIN high

2.3

 

ns

²XW/R input/output polarity selected at boot. ³ XBLAST input polarity selected at boot.

§ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

switching characteristics with external device as bus master(see Figure 31 and Figure 32)

NO.

 

PARAMETER

MIN

MAX

UNIT

 

 

 

 

 

 

11

td(XCKIH-XDLZ)

Delay time, XCLKIN high to XDx low impedance

5

 

ns

12

td(XCKIH-XDV)

Delay time, XCLKIN high to XDx valid

 

15.5

ns

13

td(XCKIH-XDIV)

Delay time, XCLKIN high to XDx invalid

5

 

ns

14

td(XCKIH-XDHZ)

Delay time, XCLKIN high to XDx high impedance

 

18

ns

15

t

Delay time, XCLKIN high to XRDY valid#

5

15.5

ns

 

d(XCKIH-XRY)

 

 

 

 

20

td(XCKIH-XRYLZ)

Delay time, XCLKIN high to XRDY low impedance

5

15.5

ns

21

td(XCKIH-XRYHZ)

Delay time, XCLKIN high to XRDY high impedance#

2P + 5 3P + 15.5

ns

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

# XRDY operates as active-low ready input/output during host-port accesses.

ADVANCE INFORMATION

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251±1443

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Texas Instruments TMS320C6202 specifications Expansion BUS Synchronous Host Port Timing, MIN MAX Unit

TMS320C6202 specifications

The Texas Instruments TMS320C6202 is a powerful digital signal processor (DSP) that is well-regarded in the realm of high-performance computing applications. As part of the TMS320C6000 family, the C6202 was designed to meet the demanding requirements of telecommunications, audio and video processing, and other real-time digital signal processing tasks.

One of the primary features of the TMS320C6202 is its superscalar architecture. This allows the processor to execute multiple instructions simultaneously, significantly improving throughput and efficiency. With two functional units, the DSP can execute both fixed-point and floating-point operations in parallel, optimizing performance for various computational workloads.

The core clock frequency of the TMS320C6202 typically reaches up to 150 MHz, which means it can process instructions at impressive speeds. This high frequency, combined with an advanced instruction set that includes efficient looping and branching instructions, makes the C6202 highly adept at handling complex algorithms common in digital signal processing.

Memory access is another critical characteristic of the TMS320C6202. It supports a unified memory architecture featuring both on-chip SRAM and external memory interfaces. This enables seamless data transfer between the processor and memory, improving overall system performance. The processor can interface with diverse memory types, including SDRAM and other high-speed memory technologies, further enhancing its versatility.

Furthermore, the TMS320C6202 incorporates a range of built-in features designed to facilitate efficient development. Its integrated hardware multipliers and accumulators allow rapid computation of mathematical functions, while on-chip debugging support simplifies the development process. Additionally, the processor features a host of peripheral interfaces, enabling integrations for input/output operations, essential for real-time applications such as multimedia processing.

Texas Instruments excels in providing software and development tools for the TMS320C6202. The Code Composer Studio (CCS) and various libraries enhance the ease of programming and optimization for this DSP, which helps engineers accelerate product development.

Overall, the Texas Instruments TMS320C6202 is a robust digital signal processor characterized by its high-speed performance, dual functional units, innovative memory architecture, and support for sophisticated algorithms. It has become a preferred choice for applications requiring intensive signal processing capabilities, making significant contributions to fields such as telecommunications, multimedia, and industrial automation.