Texas Instruments TMS320C6202 McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp =

ADVANCE INFORMATION

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1²³ (see Figure 45)

				'C6202-200
				'C6202-233
NO.				'C6202-250			UNIT
			MASTER		SLAVE
			MIN	MAX	MIN	MAX
4	tsu(DRV-CKXL)	Setup time, DR valid before CLKX low	12		2 ± 3P		ns
5	th(CKXL-DRV)	Hold time, DR valid after CLKX low	4		5 + 6P		ns

² P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

³ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1²³ (see Figure 45)

				'C6202-200
				'C6202-233
NO.		PARAMETER		'C6202-250			UNIT
			MASTER§		SLAVE
			MIN	MAX	MIN	MAX
1	t	Hold time, FSX low after CLKX high¶	H ± 2	H + 3			ns
	h(CKXH-FXL)
2	t	Delay time, FSX low to CLKX low#	T ± 2	T + 1			ns
	d(FXL-CKXL)
3	td(CKXH-DXV)	Delay time, CLKX high to DX valid	±2	4	3P + 4	5P + 17	ns
6	tdis(CKXH-DXHZ)	Disable time, DX high impedance following last data bit from	±2	4	3P + 3	5P + 17	ns
		CLKX high
7	td(FXL-DXV)	Delay time, FSX low to DX valid	L ± 2	L + 4	2P + 2	4P + 17	ns

² P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

³For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T =	CLKX period = (1 + CLKGDV) * S
H =	CLKX high pulse width	= (CLKGDV/2 + 1) * S if CLKGDV is even
		= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =	CLKX low pulse width	= (CLKGDV/2) * S if CLKGDV is even

=(CLKGDV + 1)/2 * S if CLKGDV is odd or zero

¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).

CLKX
	1	2
FSX
	6	7	3
DX	Bit 0	Bit(n-1)	(n-2)	(n-3)	(n-4)
		4	5
DR	Bit 0	Bit(n-1)	(n-2)	(n-3)	(n-4)

Figure 45. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

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