Manuals / Texas Instruments / Home Audio / Stereo System

Texas Instruments TMS320C6202 External Interrupt Timing, EXTINTx, NMI Intr Flag, INUMx

Models: TMS320C6202

1 74

Download 74 pages 1.15 Kb

Page 44

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

		EXTERNAL INTERRUPT TIMING
timing requirements for interrupt response cycles² (see Figure 25)
			'C6202-200
NO.			'C6202-233		UNIT
NO.			'C6202-250		UNIT
			'C6202-250

			MIN	MAX

2	tw(ILOW)	Width of the interrupt pulse low	2P		ns
3	tw(IHIGH)	Width of the interrupt pulse high	2P		ns

² P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

switching characteristics during interrupt response cycles² (see Figure 25)

			'C6202-200
NO.		PARAMETER	'C6202-233		UNIT
NO.		PARAMETER	'C6202-250		UNIT
			'C6202-250

			MIN	MAX

1	tR(EINTH ± IACKH)	Response time, EXT_INTx high to IACK high	9P		ns
4	td(CKO2L-IACKV)	Delay time, CLKOUT2 low to IACK valid	0	10	ns
5	td(CKO2L-INUMV)	Delay time, CLKOUT2 low to INUMx valid	0	10	ns
6	td(CKO2L-INUMIV)	Delay time, CLKOUT2 low to INUMx invalid	0	10	ns

²P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

1

CLKOUT2

3 2

EXT_INTx, NMI

Intr Flag

4

IACK

5

4

6

ADVANCE INFORMATION

INUMx

Interrupt Number

Figure 25. Interrupt Timing

44	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

Image 44

Texas Instruments TMS320C6202 specifications External Interrupt Timing, EXTINTx, NMI Intr Flag, INUMx

Contents

Advance Information FIXED-POINT Digital Signal Processor Description Device characteristicsCharacteristics Description Functional block diagram Timers Data Memory Interrupt SelectorCPU EmifCPU description Timers Bit Data C62x CPUControl RegistersLD1 Signal groups description EMU1 EMU0 RSV4 RSV3RSV2 RSV1 RSV0 Clock/PLL Ieee Standard 1149.1CE3 CE2 CE1CE0 BE3 Hold BE2XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2 Xrdy Xhold XholdaFIXED-POINT Digital Signal Processor TMS320C6202Signal PIN no TYPE² Description Name GJL GLS Expansion BUS Emif ± Address Signal PIN no TYPE² Description Name GJL GLS Emif ± Address Emif ± DataTimers Emif ± BUS ArbitrationMultichannel Buffered Serial Port 0 McBSP0 Multichannel Buffered Serial Port 1 McBSP1Reserved for Test Signal PIN no TYPE² Description Name GJL GLSMultichannel Buffered Serial Port 2 McBSP2 AD6 AE7AE8 CvddAB4 AC3AC4 AC5 CvddGND Ground PinsVSS Signal PIN no TYPE² Description Name GJL GLS Ground Pins AF10 Scsi TMDS00510WS Development supportDevelopment Tool Platform Part Number TMS Temperature Range Default 0 C to 90 C Prefix Device Speed RangeDevice Family Package Type ²Documentation support Advance Information Power-supply sequencing Clock PLLParameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Signal transition levels Parameter Measurement InformationIOL IOHInput and Output Clocks Timing requirements for CLKIN² see FigureTiming requirements for Xclkin ²³ see Figure Clkmode Unit MIN MAXSwitching characteristics for CLKOUT1²³ see Figure Switching characteristics for CLKOUT2 ³ see FigureParameter Clkmode =Switching characteristics for XFCLK²³ see Figure Xfclk TimingsAsynchronous Memory Timing AWEAOE Are AWE Ardy Setup = Strobe = Not ready = Hold =CEx BE30 EA212 ED310 SYNCHRONOUS-BURST Memory Timing Unit MIN MAXCEx BE30 BE1 BE2 BE3 BE4EA212 ED310 SDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE²Synchronous Dram Timing Timing requirements for synchronous Dram cycles see FigureRead CLKOUT2 BE1 BE2 BE3CA1 CA2 CA3 SDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE²Actv SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²Dcab SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE²SDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ² Refr CLKOUT2MRS HOLD/HOLDA Timing Timing requirements for HOLD/HOLDA cycles ² see FigureHold Holda Emif Bus² DSP Owns BusReset Timing Timing requirements for reset see FigureSwitching characteristics during reset¶ see Figure Reset CLKOUT1FIXED-POINT Digital Signal Processor INUMx External Interrupt TimingEXTINTx, NMI Intr Flag Expansion BUS Synchronous Fifo Timing MIN MAX UnitParameter MIN MAX Unit XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT §XA1 XOE XRE XWE/XWAIT³XA2 XA3XA4 XA3 XA4 XOE XRE XWE/XWAIT ³Expansion BUS Asynchronous Peripheral Timing XOE XRE XWE/XWAIT ³ XRDY§ XCEx XBE30/XA52 ² XD310XOE XRE XWE/XWAIT ³ Xrdy § Expansion BUS Synchronous Host Port Timing Xclkin XCS XAS Xcntl XW/R ² XBE30/XA52 ³Xblast § XRDY¶Xclkin XCS XAS Xcntl XW/R² XBE30/XA52³XBLAST§ XBE1 XBE2 XBE3 XBE4TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5 Xrdy XWE/XWAIT ¶ Xclkin XASXblast ³ XBE30/XA52 § Addr XD310 Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda #Expansion BUS Asynchronous Host Port Timing XCS XcntlXBE30/XA52 ² XR/W ³ XD310 Word XrdyExternal Device as Asynchronous MasterÐWrite XBE30/XA52² XR/W ³ XD310 WordXBus ² C6202 XHOLD/XHOLDA TimingDSP Owns Bus External Requestor Xhold input Expansion Bus ArbitrationÐInternal Arbiter Disabled Xhold output Xholda input XBus ² C6202Multichannel Buffered Serial Port Timing Timing requirements for McBSP²³ see FigureSwitching characteristics for McBSP²³ see Figure Clks Clkr FSR intBitn-1 ClkxFSR external CLKR/X no need to resync CLKR/Xneeds resync Timing requirements for FSR when Gsync = 1 see FigureClks Master Slave MIN MAX Master § Slave MIN MAXClkx FSX Bit Bitn-1McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = MASTER§ Slave MIN MAX FIXED-POINT Digital Signal Processor McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = DMAC, TIMER, POWER-DOWN Timing Switching characteristics for Dmac outputs² see FigureTiming requirements for timer inputs ² see Figure Switching characteristics for timer outputs² see FigureSwitching characteristics for power-down outputs² see Figure TwPDH Pulse duration, PD high 10PSwitching characteristics for Jtag test port see Figure DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing Timing requirements for Jtag test port see FigureThermal resistance characteristics S-PBGA package Mechanical Data18,10 16,80 TYP 17,90 Heat Slug80 MAX 4188959/B 12/98Important Notice