Texas Instruments TMS320C6202 specifications Synchronous Dram Timing

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

SYNCHRONOUS DRAM TIMING

timing requirements for synchronous DRAM cycles (see Figure 17)

NO.			'C6202-200		'C6202-233		'C6202-250		UNIT
			MIN	MAX	MIN	MAX	MIN	MAX
7	tsu(EDV-CKO2H)	Setup time, read EDx valid before CLKOUT2 high	1		1		0.5		ns
8	th(CKO2H-EDV)	Hold time, read EDx valid after CLKOUT2 high	3		3		3		ns

switching characteristics for synchronous DRAM cycles²³ (see Figure 17±Figure 22)

NO.

PARAMETER

'C6202-200

'C6202-233

'C6202-250

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Output setup time,

valid

1

tosu(CEV-CKO2H)

CEx

2P ± 6

2P ± 4.6

2P ± 4

ns

before CLKOUT2 high

2

toh(CKO2H-CEV)

Output hold time,

CEx

valid after

1.5

1.5

1.5

ns

CLKOUT2 high

Output setup time,

valid

3

tosu(BEV-CKO2H)

BEx

2P ± 6

2P ± 4.6

2P ± 4

ns

before CLKOUT2 high

Output hold time,

invalid after

4

toh(CKO2H-BEIV)

BEx

1.5

1.5

1.5

ns

CLKOUT2 high

5

tosu(EAV-CKO2H)

Output setup time, EAx valid

2P ± 6

2P ± 4.6

2P ± 4

ns

before CLKOUT2 high

6

toh(CKO2H-EAIV)

Output hold time, EAx invalid after

1.5

1.5

1.5

ns

CLKOUT2 high

Output setup time,

9

tosu(CASV-CKO2H)

SDCAS/SSADS valid before

2P ± 6

2P ± 4.6

2P ± 4

ns

CLKOUT2 high

Output hold time,

10

toh(CKO2H-CASV)

SDCAS/SSADS

1.5

1.5

1.5

ns

valid after CLKOUT2 high

11

tosu(EDV-CKO2H)

Output setup time, EDx valid

2P ± 6

2P ± 4.6

2P ± 4

ns

before CLKOUT2 high§

12

toh(CKO2H-EDIV)

Output hold time, EDx invalid after

1.5

1.5

1.5

ns

CLKOUT2 high

13

tosu(WEV-CKO2H)

Output setup time,

SDWE/SSWE

2P ± 6

2P ± 4.6

2P ± 4

ns

valid before CLKOUT2 high

Output hold time,

14

toh(CKO2H-WEV)

SDWE/SSWE

1.5

1.5

1.5

ns

valid after CLKOUT2 high

15

tosu(SDA10V-CKO2H)

Output setup time, SDA10 valid

2P ± 6

2P ± 4.6

2P ± 4

ns

before CLKOUT2 high

16

toh(CKO2H-SDA10IV)

Output hold time, SDA10 invalid

1.5

1.5

1.5

ns

after CLKOUT2 high

Output setup time,

17

tosu(RASV-CKO2H)

SDRAS/SSOE

2P ± 6

2P ± 4.6

2P ± 4

ns

valid before CLKOUT2 high

Output hold time,

18

toh(CKO2H-RASV)

SDRAS/SSOE

1.5

1.5

1.5

ns

valid after CLKOUT2 high

²P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

³ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time.

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