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Texas Instruments TMS320C6202 specifications Emif ± BUS Arbitration, Timers

Models: TMS320C6202

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									TMS320C6202
									FIXED-POINT DIGITAL SIGNAL PROCESSOR
									SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

								Signal Descriptions (Continued)

		SIGNAL			PIN NO.		TYPE²		DESCRIPTION
				NAME	GJL	GLS	TYPE²		DESCRIPTION
				NAME	GJL	GLS

							EMIF ± ASYNCHRONOUS MEMORY CONTROL

	ARE				V24	T21	O/Z		Asynchronous memory read enable

					V25	R20	O/Z		Asynchronous memory output enable
	AOE				V25	R20	O/Z		Asynchronous memory output enable

					U23	T22	O/Z		Asynchronous memory write enable
	AWE				U23	T22	O/Z		Asynchronous memory write enable

	ARDY				W25	T20	I		Asynchronous memory ready input

EMIF ± SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL

SDA10

AE21

AA19

O/Z

SDRAM address 10 (separate for deactivate command)

AE22

AB21

O/Z

SDRAM column-address strobe/SBSRAM address strobe

SDCAS/SSADS

AF22

Y19

O/Z

SDRAM row-address strobe/SBSRAM output enable

SDRAS/SSOE

AC20

AA20

O/Z

SDRAM write enable/SBSRAM write enable

SDWE/SSWE

EMIF ± BUS ARBITRATION

HOLD

Y26

V22

I

Hold request from the host

V23

U21

O

Hold-request-acknowledge to the host

HOLDA

TIMERS

TOUT1

J4

F2

O

Timer 1 or general-purpose output

TINP1

G2

F3

I

Timer 1 or general-purpose input

TOUT0

F1

D1

O

Timer 0 or general-purpose output

TINP0

H4

E2

I

Timer 0 or general-purpose input

DMA ACTION COMPLETE STATUS

DMAC3

Y3

V3

DMAC2

AA2

W2

O

DMA action complete

DMAC1

AB1

AA1

DMAC0

AA3

W3

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)

CLKS0

M4

K3

I

External clock source (as opposed to internal)

CLKR0

M2

L2

I/O/Z

Receive clock

CLKX0

M3

K1

I/O/Z

Transmit clock

DR0

R2

M2

I

Receive data

DX0

P4

M3

O/Z

Transmit data

FSR0

N3

M1

I/O/Z

Receive frame sync

FSX0

N4

L3

I/O/Z

Transmit frame sync

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

CLKS1

G1

E1

I

External clock source (as opposed to internal)

CLKR1

J3

G2

I/O/Z

Receive clock

CLKX1

H2

G3

I/O/Z

Transmit clock

DR1

L4

H1

I

Receive data

DX1

J1

H2

O/Z

Transmit data

FSR1

J2

H3

I/O/Z

Receive frame sync

FSX1

K4

G1

I/O/Z

Transmit frame sync

² I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

ADVANCE INFORMATION

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

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Texas Instruments TMS320C6202 specifications Emif ± BUS Arbitration, Timers, Multichannel Buffered Serial Port 0 McBSP0

Contents

Advance Information FIXED-POINT Digital Signal Processor Device characteristics Characteristics DescriptionDescription Emif Functional block diagramTimers Data Memory Interrupt Selector CPUCPU description Registers TimersBit Data C62x CPU ControlLD1 Clock/PLL Ieee Standard 1149.1 Signal groups descriptionEMU1 EMU0 RSV4 RSV3 RSV2 RSV1 RSV0BE3 Hold BE2 CE3 CE2CE1 CE0Xrdy Xhold Xholda XD310 XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2TMS320C6202 FIXED-POINT Digital Signal ProcessorSignal PIN no TYPE² Description Name GJL GLS Expansion BUS Emif ± Address Emif ± Data Signal PIN no TYPE² Description Name GJL GLS Emif ± AddressMultichannel Buffered Serial Port 1 McBSP1 TimersEmif ± BUS Arbitration Multichannel Buffered Serial Port 0 McBSP0Signal PIN no TYPE² Description Name GJL GLS Multichannel Buffered Serial Port 2 McBSP2Reserved for Test Cvdd AD6AE7 AE8AC5 Cvdd AB4AC3 AC4Ground Pins VSSGND Signal PIN no TYPE² Description Name GJL GLS Ground Pins AF10 Development support Development Tool Platform Part NumberScsi TMDS00510WS TMS Package Type ² Temperature Range Default 0 C to 90 CPrefix Device Speed Range Device FamilyDocumentation support Advance Information Clock PLL Power-supply sequencingRecommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit IOH Signal transition levelsParameter Measurement Information IOLClkmode Unit MIN MAX Input and Output ClocksTiming requirements for CLKIN² see Figure Timing requirements for Xclkin ²³ see FigureClkmode = Switching characteristics for CLKOUT1²³ see FigureSwitching characteristics for CLKOUT2 ³ see Figure ParameterXfclk Timings Switching characteristics for XFCLK²³ see FigureAWE Asynchronous Memory TimingSetup = Strobe = Not ready = Hold = CEx BE30 EA212 ED310AOE Are AWE Ardy Unit MIN MAX SYNCHRONOUS-BURST Memory TimingSDCAS/SSADS² SDRAS/SSOE² SDWE/SSWE² CEx BE30BE1 BE2 BE3 BE4 EA212 ED310Timing requirements for synchronous Dram cycles see Figure Synchronous Dram TimingSDA10 SDRAS/SSOE ² SDCAS/SSADS² SDWE/SSWE² Read CLKOUT2BE1 BE2 BE3 CA1 CA2 CA3SDA10 SDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE² ActvSDRAS/SSOE² SDCAS/SSADS² SDWE/SSWE² DcabRefr CLKOUT2 MRSSDA10 SDRAS/SSOE ² SDCAS/SSADS ² SDWE/SSWE ² Emif Bus² DSP Owns Bus HOLD/HOLDA TimingTiming requirements for HOLD/HOLDA cycles ² see Figure Hold HoldaReset CLKOUT1 Reset TimingTiming requirements for reset see Figure Switching characteristics during reset¶ see FigureFIXED-POINT Digital Signal Processor External Interrupt Timing EXTINTx, NMI Intr FlagINUMx XA1 XA2 XA3 XA4 XOE XRE XWE/XWAIT § Expansion BUS Synchronous Fifo TimingMIN MAX Unit Parameter MIN MAX UnitXA3 XA4 XOE XRE XWE/XWAIT ³ XA1XOE XRE XWE/XWAIT³ XA2 XA3XA4Expansion BUS Asynchronous Peripheral Timing XCEx XBE30/XA52 ² XD310 XOE XRE XWE/XWAIT ³ Xrdy §XOE XRE XWE/XWAIT ³ XRDY§ Expansion BUS Synchronous Host Port Timing XRDY¶ Xclkin XCS XAS XcntlXW/R ² XBE30/XA52 ³ Xblast §XBE1 XBE2 XBE3 XBE4 Xclkin XCS XAS Xcntl XW/R²XBE30/XA52³ XBLAST§TdXCKIH-XASV Delay time, Xclkin high to Valid 15.5 Xclkin XAS Xblast ³Xrdy XWE/XWAIT ¶ Xrdy Xboff Xhold ¶ Xholda ¶ Xhold # Xholda # XBE30/XA52 § Addr XD310Xrdy Expansion BUS Asynchronous Host Port TimingXCS Xcntl XBE30/XA52 ² XR/W ³ XD310 WordXBE30/XA52² XR/W ³ XD310 Word External Device as Asynchronous MasterÐWriteXHOLD/XHOLDA Timing DSP Owns Bus External Requestor Xhold inputXBus ² C6202 Xhold output Xholda input XBus ² C6202 Expansion Bus ArbitrationÐInternal Arbiter DisabledTiming requirements for McBSP²³ see Figure Multichannel Buffered Serial Port TimingSwitching characteristics for McBSP²³ see Figure Clkx Clks ClkrFSR int Bitn-1Timing requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/Xneeds resync Master § Slave MIN MAX Master Slave MIN MAXBit Bitn-1 Clkx FSXMcBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = MASTER§ Slave MIN MAX FIXED-POINT Digital Signal Processor McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Switching characteristics for timer outputs² see Figure DMAC, TIMER, POWER-DOWN TimingSwitching characteristics for Dmac outputs² see Figure Timing requirements for timer inputs ² see FigureTwPDH Pulse duration, PD high 10P Switching characteristics for power-down outputs² see FigureTiming requirements for Jtag test port see Figure Switching characteristics for Jtag test port see FigureDTCKL-TDOV Delay time, TCK low to TDO valid Jtag TEST-PORT TimingMechanical Data Thermal resistance characteristics S-PBGA package4188959/B 12/98 18,10 16,80 TYP 17,90Heat Slug 80 MAXImportant Notice