Texas Instruments TMS320C6202 specifications SYNCHRONOUS-BURST Memory Timing, Unit MIN MAX

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

SYNCHRONOUS-BURST MEMORY TIMING

timing requirements for synchronous-burst SRAM cycles (see Figure 15)

NO.			'C6202-200	'C6202-233	'C6202-250		UNIT
			MIN MAX	MIN MAX	MIN	MAX
7	tsu(EDV-CKO2H)	Setup time, read EDx valid before CLKOUT2	2.5	2.1	2		ns
		high
8	th(CKO2H-EDV)Hold time, read EDx valid after CLKOUT2 high		1.5	1.5	1.5		ns

switching characteristics for synchronous-burst SRAM cycles²³ (see Figure 15 and Figure 16)

NO.

PARAMETER

'C6202-200

'C6202-233

'C6202-250

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Output setup time,

valid

1

tosu(CEV-CKO2H)

CEx

2P ± 5.5

2P ± 4.4

2P ± 3.8

ns

before CLKOUT2 high

Output hold time,

valid after

2

toh(CKO2H-CEV)

CEx

1

1

1

ns

INFORMATION

CLKOUT2 high

3

tosu(BEV-CKO2H)

Output setup time,

BEx

valid

2P ± 5.5

2P ± 4.4

2P ± 3.8

ns

before CLKOUT2 high

Output hold time,

invalid

4

toh(CKO2H-BEIV)

BEx

1

1

1

ns

after CLKOUT2 high

5

tosu(EAV-CKO2H)

Output setup time, EAx valid

2P ± 5.5

2P ± 4.4

2P ± 3.8

ns

before CLKOUT2 high

6

toh(CKO2H-EAIV)

Output hold time, EAx invalid

1

1

1

ns

after CLKOUT2 high

Output setup time,

9

tosu(ADSV-CKO2H)

SDCAS/SSADS valid before

2P ± 5.5

2P ± 4.4

2P ± 3.8

ns

ADVANCE

CLKOUT2 high

Output hold time,

10

toh(CKO2H-ADSV)

SDCAS/SSADS valid after

1

1

1

ns

CLKOUT2 high

Output setup time,

11

tosu(OEV-CKO2H)

SDRAS/SSOE valid before

2P ± 5.5

2P ± 4.4

2P ± 3.8

ns

CLKOUT2 high

Output hold time,

12

toh(CKO2H-OEV)

SDRAS/SSOE

1

1

1

ns

valid after CLKOUT2 high

13

tosu(EDV-CKO2H)

Output setup time, EDx valid

2P ± 5.5

2P ± 4.4

2P ± 3.8

ns

before CLKOUT2 high§

14

toh(CKO2H-EDIV)

Output hold time, EDx invalid

1

1

1

ns

after CLKOUT2 high

Output setup time,

15

tosu(WEV-CKO2H)

SDWE/SSWE

2P ± 5.5

2P ± 4.4

2P ± 3.8

ns

valid before CLKOUT2 high

Output hold time,

16

toh(CKO2H-WEV)

SDWE/SSWE

1

1

1

ns

valid after CLKOUT2 high

²P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

³ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.

§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time.

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