Texas Instruments TMS320C6202 specifications Expansion BUS Synchronous Fifo Timing, MIN MAX Unit

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

EXPANSION BUS SYNCHRONOUS FIFO TIMING

timing requirements for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28)

NO.			MIN	MAX	UNIT
5	tsu(XDV-XFCKH)	Setup time, read XDx valid before XFCLK high	2.5		ns
6	th(XFCKH-XDV)	Hold time, read XDx valid after XFCLK high	2		ns

switching characteristics for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28)

NO.		PARAMETER					MIN	MAX	UNIT
1	td(XFCKH-XCEV)	Delay time, XFCLK high to				valid	1.5	5.2	ns
				XCEx
2	t	Delay time, XFCLK high to					1.5	5.2	ns
				XBE[3:0]/XA[5:2] valid²
	d(XFCKH-XAV)
3	td(XFCKH-XOEV)	Delay time, XFCLK high to			valid		1.5	5.2	ns
				XOE
4	td(XFCKH-XREV)	Delay time, XFCLK high to			valid		1.5	5.2	ns
				XRE
7	t	Delay time, XFCLK high to					1.5	5.2	ns
			XWE/XWAIT³ valid
	d(XFCKH-XWEV)
8	td(XFCKH-XDV)	Delay time, XFCLK high to XDx valid						5.2	ns
9	td(XFCKH-XDIV)	Delay time, XFCLK high to XDx invalid					1.5		ns

²XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses. ³ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

XFCLK
	1				1
XCE3²
XBE[3:0]/XA[5:2]³	2				2
	XA1	XA2	XA3		XA4
	3				3
XOE
	4				4
XRE
XWE/XWAIT§			6
		5
XD[31:0]		D1	D2	D3	D4

² FIFO read (glueless) mode only available in XCE3.

³XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses. § XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

Figure 26. FIFO Read Timing (Glueless Read Mode)

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