Texas Instruments TMS320C6202 specifications HOLD/HOLDA Timing, Hold Holda, Emif Bus² DSP Owns Bus

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

HOLD/HOLDA TIMING

timing requirements for the

HOLD/HOLDA cycles² (see Figure 23)

'C6202-200

NO.

'C6202-233

UNIT

'C6202-250

MIN

MAX

3

t

Hold time,

low after

low

P

ns

oh(HOLDAL-HOLDL)

HOLD

HOLDA

²P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

switching characteristics for the HOLD/HOLDA cycles²³ (see Figure 23)

									'C6202-200
NO.		PARAMETER							'C6202-233		UNIT
									'C6202-250
									MIN	MAX
1	tR(HOLDL-EMHZ)	Response time,		low to EMIF Bus high impedance					4P	§	ns
			HOLD
2	td(EMHZ-HOLDAL)	Delay time, EMIF Bus high impedance to						low	0	2P	ns
						HOLDA
4	tR(HOLDH-EMLZ)	Response time,		high to EMIF Bus low impedance					3P	7P	ns
			HOLD
5	td(EMLZ-HOLDAH)	Delay time, EMIF Bus low impedance to					high		0	2P	ns
					HOLDA

²P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

³EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10. § All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with

external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

INFORMATION

HOLD

HOLDA

EMIF Bus²

DSP Owns Bus	External Requestor	DSP Owns Bus
	Owns Bus
	3
2		5
1		4
C6202		C6202

ADVANCE

² EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.

Figure 23. HOLD/HOLDA Timing

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