Texas Instruments TMS320C6202 specifications Multichannel Buffered Serial Port Timing

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B ± AUGUST 1998 ± REVISED AUGUST 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING

timing requirements for McBSP²³ (see Figure 40)

				'C6202-200
NO.				'C6202-233		UNIT
				'C6202-250
				MIN	MAX
2	tc(CKRX)	Cycle time, CLKR/X	CLKR/X ext	2P		ns
3	tw(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X ext	P ± 1		ns
5	tsu(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR int	9		ns
			CLKR ext	1
6	th(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR int	6		ns
			CLKR ext	3
7	tsu(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR int	8		ns
			CLKR ext	0
8	th(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR int	3		ns
			CLKR ext	3
10	tsu(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX int	9		ns
			CLKX ext	1
11	th(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX int	6		ns
			CLKX ext	3

²CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ³ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

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