Texas Instruments TMS320F20x/F24x DSP manuals

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Texas Instruments TMS320F20x/F24x DSP Manual

Texas Instruments TMS320F20x/F24x DSP Manual

108 pages322.5 Kb

Preface
3Read This First
- About This Manual
  - Related Documenta- tion from Texas Instruments
- How to Use This Manual
- 4Notational Conventions
- 5Related Documentation From Texas Instruments
  - If You Need Assistance . . .
    - vii
  - Read This First
- 7If You Need Assistance . . .
9Contents
11Figures
12Tables
13Introduction
- Chapter 1
  - in-system
  - 141.1 Basic Concepts of Flash Memory Technology
    - flash operation
    - block
  - 151.2 TMS320F20x/F24x Flash Module
    - Table 11. TMS320 Devices With On-Chip Flash EEPROM
      - TMS320F20x/F24x Flash Module
    - 16Figure 11. TMS320F20x/F24x Program Space Memory Maps
  - 171.3 Benefits of Embedded Flash Memory in a DSP System
19Flash Operations and Control Registers
- Chapter 2
  - 202.1 Operations that Modify the Contents of the F20x/F24x Flash Array
    - Operations that Modify the Contents of the F20x/F24x Flash Array
    - 22Figure 21. Flash Memory Logic Levels During Programming and Erasing
    - Table 21. Operations that Modify the Contents of the Flash Array
  - 232.2 Accessing the Flash Module
    - 24Figure 22. Memory Maps in Register and Array Access Modes
      - 2.2.1 TMS320F206 Flash Access-Control Register
      - 252.2.2 TMS320F24x Flash Access-Control Register
        Flash Module Control Registers
  - 262.3 Flash Module Control Registers
    - Table 22. Flash Module Control Registers
      - 2.3.1 Segment Control Register (SEG_CTR)
    - Figure 23. Segment Control Register (SEG_CTR)
      - Flash Module Control Registers
      - Flash Operations and Control Registers
    - 27Table 23. Segment Control Register Field Descriptions
    - 28Table 24. Flash Array Segments Summary
      - 2.3.2 Flash Test Register (TST)
      - 2.3.3 Write Address Register (WADRS)
  - 302.4 Read Modes
  - 312.5 Program Operation
    - pro- gram pulse
  - 322.6 Erase Operation
    - clearing the array
    - erase pulse
    - Flash Memory Logic Lev- els During Programming and Erasing
  - 332.7 Recovering From Over-Erasure (Flash-Write Operation)
    - flash-write pulse
    - Flash Memory Logic Levels During Programming and Erasing
  - 342.8 Reading From the Flash Array
  - 2.9 Protecting the Array
35Algorithm Implementations and Software Considerations
- Chapter 3
  - 363.1 How the Algorithms Fit Into the Program-Erase-Reprogram Flow
    - How the Algorithms Fit Into the Program-Erase-Reprogram Flow
    - 37Figure 31. Algorithms in the Overall Flow
  - 383.2 Programming (or Clear) Algorithm
    - Figure 32. The Programming Algorithm in the Overall Flow
      - 39s
        3-6
    - 40Figure 33. Programming or Clear Algorithm Flow
    - 41Table 31. Steps for Verifying Programmed Bits and Applying One Program or Clear Pulse
    - 42Table 31. Steps for Verifying Programmed Bits and Applying One Program or Clear Pulse (Continued)
      - Erase Algorithm
  - 443.3 Erase Algorithm
    - Figure 34. Erase Algorithm in the Overall Flow
    - 45Table 32. Steps for Applying One Erase Pulse
      - address complementing
        Erase Algorithm
    - 47Figure 35. Erase Algorithm Flow
  - 483.4 Flash-Write Algorithm
    - Figure 36. Flash-Write Algorithm in the Overall Flow
      - flash-write pulse
        Flash-Write Algorithm
    - 49Table 33. Steps for Applying One Flash-Write Pulse
      - , on page 2-12.
        Flash-Write Algorithm
    - 50Figure 37. Flash-Write Algorithm Flow
- Appendix A
53Assembly Source Listings and Program Examples
- 54A.1 Assembly Source for Algorithms
  - A.1.1 Header File for Constants and Variables, SVAR20.H
  - 57A.1.2 Clear Algorithm, SCLR20.ASM
  - 62A.1.3 Erase Algorithm, SERA20.ASM
  - 67A.1.4 Flash-Write Algorithm, SFLW20.ASM
  - 71A.1.5 Programming Algorithm, SPGM20.ASM
  - 77A.1.6 Subroutines Used By All Four Algorithms, SUTILS20.ASM
    - 78.end
- 79A.2 C-Callable Interface to Flash Algorithms
- 84A.3 Sample Assembly Code to Erase and Reprogram the TMS320F206
  - A.3.1 Assembly Code for TMS320F206
  - 87A.3.2 Linker Command File for TMS320F206 Sample Assembly Code
    - 88Sample Assembly Code to Erase and Reprogram the TMS320F206
- 89A.4 Sample C Code to Erase and Reprogram the TMS320F206
  - C-Callable Interface to Flash Algorithms
  - Using the Algo- rithms With Assembly Code
    - .
  - A.4.1 C Code That Calls the Interface to Flash Algorithms for TMS320F206
  - 90A.4.2 Linker Command File for TMS320F206 Sample C Code
- 92A.5 Sample Assembly Code to Erase and Reprogram the TMS320F240
  - A.5.1 Assembly Code for TMS320F240
  - 97A.5.2 Linker Command File for TMS320F240 Sample Assembly Code
- 99A.6 Using the Algorithms With C Code to Erase and Reprogram the F240
  - C-Callable Interface to Flash Algorithms
  - Using the Algorithms With Assembly Code
  - A.6.1 C Code That Calls the Interface to Flash Algorithms for TMS320F240
  - 100A.6.2 Linker Command File for TMS320F240 Sample C Code
  - 102A.6.3 C Function for Disabling TMS320F240 Watchdog Timer
  - 103A.6.4 C Functions for Initializing the TMS320F240
105Index
- A
- B
- C
- D
- E
- 106F
- G
- H
- I
- K
- L
- 107M
- N
- O
- P
- R
- S
- 108T
- U
- V
- W

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