Texas Instruments TMS320F20x/F24x DSP specs

PRELIMINARY

AppendixAppendixAA

Assembly Source Listings and

Program Examples

The flash array is erased and programmed by code running on the DSP core. This code can originate from off-chip memory or can be loaded into on-chip RAM. The available flash programming tools for the 'F20x/F24x allow you to program the on-chip flash module without having knowledge or visibility of the algorithms. One scheme uses the scan emulation feature of the 'F20x/F24x to load the algorithms onto the DSP and control execution, and another scheme relies on boot loader code preprogrammed into the flash memory at the facto- ry. You can find more information about these stand-alone flash programming tools on the Texas Instruments web page at http://www.ti.com. This appendix explains how to use the algorithm source files to program the flash module. You need this information to create new flash programming tools or to add such features as remote reprogrammability to a design.

Topic		Page

A.1	Assembly Source for Algorithms	. . A-2
A.2	C-Callable Interface to Flash Algorithms	. A-27
A.3	Sample Assembly Code to Erase and Reprogram
	the TMS320F206	. A-32
A.4	Sample C Code to Erase and Reprogram the TMS320F206	. A-37
A.5	Sample Assembly Code to Erase and Reprogram
	the TMS320F240	. A-40
A.6	Using the Algorithms with C Code to Erase and Reprogram the
	TMS320F240	. A-47

PRELIMINARY

A-1

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Texas Instruments TMS320F20x/F24x DSP manual Assembly Source Listings Program Examples

Contents

Literature Number SPRU282 September Important Notice Read This First Preliminary Related Documentation From Texas Instruments Preliminary If You Need Assistance Viii Contents Contents Figures Tables Introduction Basic Concepts of Flash Memory Technology ±1. TMS320 Devices With On-Chip Flash Eeprom TMS320F20x/F24x Flash Module ±1. TMS320F20x/F24x Program Space Memory Maps Benefits of Embedded Flash Memory in a DSP System Preliminary Topic Flash Operations and Control Registers Preliminary Flash Operations and Control Registers ±1. Flash Memory Logic Levels During Programming and Erasing Accessing the Flash Module 1 TMS320F206 Flash Access-Control Register ±2. Memory Maps in Register and Array Access Modes OUT 2 TMS320F24x Flash Access-Control Register Segment Control Register Segctr Flash Module Control Registers ±3. Segment Control Register Field Descriptions Write Address Register Wadrs Flash Test Register TST Write Data Register Wdata Read Modes Program Operation Erase Operation Recovering From Over-Erasure Flash-Write Operation Protecting the Array Reading From the Flash Array Algorithm Implementations Software Considerations How the Algorithms Fit Into the Program-Erase-Reprogram Flow ±1. Algorithms in the Overall Flow ±2. The Programming Algorithm in the Overall Flow Programming or Clear Algorithm Preliminary ±3. Programming or Clear Algorithm Flow Step Action Description Mask the data to program Preliminary ±4. Erase Algorithm in the Overall Flow Erase Algorithm ±2. Steps for Applying One Erase Pulse Preliminary ±5. Erase Algorithm Flow ±6. Flash-Write Algorithm in the Overall Flow Flash-Write Algorithm ±3. Steps for Applying One Flash-Write Pulse ±7. Flash-Write Algorithm Flow Preliminary Preliminary Assembly Source Listings Program Examples Header File for Constants and Variables, SVAR20.H Assembly Source for Algorithms BASE0 ErrorBASE+0 BASE1 D5K ConstantsD7K Dloop Segst Clear Algorithm, SCLR20.ASMSegend Protect Splk #0,ERROR Gclr PROTECT,SEGST,SEGEND DELAY,REGS,ARRAYAR0 AR1 Sacl Flst Exit Splk #1,ERRORLacl Fladrs Newrow SET Delay Call DELAY,*,AR6 Wait Stop Write Operation Splk Activate Write BIT Tblw SPAD1 Execute Command LARShutdown Write Operation Tblw SPAD1 Execute Command LAR Tblr Fldata Prgbyte Call SETRDVER0 Tblw SPAD1 Execute Command LARLacl BASE2 Bcnd PBDONE,EQ Erase Algorithm, SERA20.ASM Erase Exebin Command Word Erase Command WordInverse Erase Command Word Flash Write Command Word Sacl Flend Clrc OVMCall Setmode Xorerase Inverase Splk #INVER,BASE0 Call Setmode Splk #STOP,BASE0Bldd Nextivers Lacl BASE1 Flash Stop command, and Ffff for Wdata Flash-Write Algorithm, SFLW20.ASM Bldd #FLST,BASE1 MaxflwFlws Call DELAY,*,AR6 Call Array Access Flash Array DoneBcnd Flwrite Splk Setmode Call Lacl Tblw LAR Call Call RET LAR AR0,#MAXFLW Cmpr Programming Algorithm, SPGM20.ASM AR3 PROTECT,DELAY,REGS,ARRAYAR4 Gpgmj Gpgmj Splk Setc Intm Globally Mask ALL Interrupts Splk #0,ERRORMask ALL Interrupts SUB Sacl BASE4 Bcnd DONE, GT Rowdone Lacl FladrsLacl Fladrs Newrow Adjrow NEG SETRDVER0 Call Regs Access Flash Registers Shut Down Write Operation Tblw SPAD1 Execute Command LAR Pbend RET XOR FldataBcnd PBEND,EQ Subroutines Used By All Four Algorithms, SUTILS20.ASM SPAD2,FACCESS1 OUT SPAD2,FACCESS0OUT SPAD2,F24XACCS Lacc Flst SUB Callable Interface to Flash Algorithms SEGST,SEGEND,PROTECT GclrPARMS+1 PARMS+2 Ersparams Lacl ErrorArstack Arprotect Call Flws Sacl ErscountLAR AR1,SVAR1 1PROTECT Call Gpgmj Popd *+ Assembly Code for TMS320F206 Sample Assembly Code to Erase and Reprogram the TMS320F206 PARMS+1 SUB Memory Sections Block B2Psaram DLY Psaram Sample C Code to Erase and Reprogram the TMS320F206 Linker Command File for TMS320F206 Sample C Code FLASH1 FLASH0BLKB2 Block B2 Dsaram Assembly Code for TMS320F240 Sample Assembly Code to Erase and Reprogram the TMS320F240 Wdcr RticrCKCR0 CKCR1 PORRST, PLLRST, Illrst SWRST, Wdrst Lacl Syssr Accl = Syssr LDP #DPPF1Sacl Syssr LDP #PARMS Splk Daram LDP #PARMS B0PGM Linker Command File for TMS320F240 Sample Assembly CodeExtram Extram 0 /******Delay Subroutine Rev1.003/98 JGC Linker Command File for TMS320F240 Sample C Code B0DAT Block B2 Dsram Lacl Wdcr Function for Disabling TMS320F240 Watchdog TimerCompute Length Sacl Wdcr Functions for Initializing the TMS320F240Pshd Syscr Sacl Wdtcr Index Assembly code SERA2x.ASM Described 10 to Margin Role in single program pulse WRITE/ERASE field Described