Texas Instruments TMS320F20x/F24x DSP ±1. Operations that Modify the Contents of the Flash Array

Operations that Modify the Contents of the 'F20x/F24x Flash Array

PRELIMINARY

Figure 2±1. Flash Memory Logic Levels During Programming and Erasing

Depletion Mode

Inverse Erase

Reference Level

Logic 1

VER1

Reference Level

1 Margin

SErase

(Towards logic

one level)

Erase operation

0 Margin

VER0

Reference level

Logic 0

Program operations

SClear

SProgram

SFlash Write

(Towards logic zero level)

Table 2±1. Operations that Modify the Contents of the Flash Array

Change in Bit Level

Towards Logic 1		Towards Logic 0
Function	Reference	Function	Reference
	Level		Level
Erase (all bits)	VER1	Program (selected bits)	VER0
		Clear (all bits)	VER0
		Flash-Write (all bits)	Inverse Erase

2-4 PRELIMINARY