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Texas Instruments TMS320F20x/F24x DSP manual Figures

Models: TMS320F20x/F24x DSP

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1±1	TMS320F20x/F24x Program Space Memory Maps	. . . . . . . . . . . 14
2±1	Flash Memory Logic Levels During Programming and Erasing	. . . . . . . . . . . 24
2±2	Memory Maps in Register and Array Access Modes	. . . . . . . . . . . 26
2±3	Segment Control Register (SEG_CTR)	. . . . . . . . . . . 28
3±1	Algorithms in the Overall Flow	. . . . . . . . . . . 33
3±2	The Programming Algorithm in the Overall Flow	. . . . . . . . . . . 34
3±3	Programming or Clear Algorithm Flow	. . . . . . . . . . . 3-6
3±4	Erase Algorithm in the Overall Flow	. . . . . . . . . . 310
3±5	Erase Algorithm Flow	. . . . . . . . . . 313
3±6	Flash-Write Algorithm in the Overall Flow	. . . . . . . . . . 314
3±7	Flash-Write Algorithm Flow	. . . . . . . . . . 316

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Texas Instruments TMS320F20x/F24x DSP manual Figures

Contents

Printed on Recycled Paper TMS320F20x/F24x DSP Embedded Flash Memory Technical ReferenceLiterature Number SPRU282 September IMPORTANT NOTICE About This Manual How to Use This ManualRead This First PRELIMINARYThis document uses the following conventions PRELIMINARYNotational Conventions PRELIMINARYPRELIMINARY Related Documentation From Texas InstrumentsPRELIMINARY PRELIMINARY TMS320C2xx C Source Debugger Users Guide literature number SPRU151 tells you how to invoke the C2xx emulator and simulator ver- sions of the C source debugger interface. This book discusses various aspects of the debugger interface, including window management, com- mand entry, code execution, data management, and breakpoints. It also includes a tutorial that introduces basic debugger functionalityPRELIMINARY Europe, Middle East, Africa If You Need AssistanceWorld-Wide Web Sites North America, South America, Central AmericaPRELIMINARY PRELIMINARY2 Flash Operations and Control Registers Contents1 Introduction A.1.1 Header File for Constants and Variables, SVAR20.H . . . . . . . . . . . . . . . . . . . . . A2 A.1.2 Clear Algorithm, SCLR20.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A5 A.1.3 Erase Algorithm, SERA20.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A10 A.1.4 Flash-Write Algorithm, SFLW20.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A15 A.1.5 Programming Algorithm, SPGM20.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A19 A.1.6 Subroutines Used By All Four Algorithms, SUTILS20.ASM . . . . . . . . . . . . . . . A25 Figures 2±2 Flash Module Control Registers Tables2±1 Operations that Modify the Contents of the Flash Array 1±1 TMS320 Devices With On-Chip Flash EEPROMTopic IntroductionChapter PagePRELIMINARY 1.1 Basic Concepts of Flash Memory TechnologyPRELIMINARY PRELIMINARY 1.2 TMS320F20x/F24x Flash ModuleTable 1±1. TMS320 Devices With On-Chip Flash EEPROM PRELIMINARYTMS320F20x/F24x Flash Module Figure 1±1. TMS320F20x/F24x Program Space Memory MapsPRELIMINARY PRELIMINARYPRELIMINARY 1.3 Benefits of Embedded Flash Memory in a DSP SystemPRELIMINARY PRELIMINARY PRELIMINARYChapter TopicPage Flash Operations and Control RegistersPRELIMINARY 2.1 Operations that Modify the Contents of the F20x/F24x Flash ArrayPRELIMINARY PRELIMINARY This procedure is discussed in complete detail in ChapterPRELIMINARY PRELIMINARY Table 2±1. Operations that Modify the Contents of the Flash ArrayFigure 2±1. Flash Memory Logic Levels During Programming and Erasing Operations that Modify the Contents of the F20x/F24x Flash ArrayPRELIMINARY 2.2 Accessing the Flash ModulePRELIMINARY PRELIMINARY Figure 2±2. Memory Maps in Register and Array Access Modes2.2.1 TMS320F206 Flash Access-Control Register PRELIMINARYPRELIMINARY 2.2.2 TMS320F24x Flash Access-Control RegisterPRELIMINARY Figure 2±3. Segment Control Register SEGCTR 2.3 Flash Module Control RegistersTable 2±2. Flash Module Control Registers 2.3.1 Segment Control Register SEGCTRFlash Module Control Registers Table 2±3. Segment Control Register Field DescriptionsPRELIMINARY PRELIMINARYPRELIMINARY Table 2±4. Flash Array Segments Summary2.3.2 Flash Test Register TST 2.3.3 Write Address Register WADRSPRELIMINARY 2.3.4 Write Data Register WDATAPRELIMINARY PRELIMINARY 2.4 Read ModesPRELIMINARY PRELIMINARY 2.5 Program OperationPRELIMINARY Erase Operation 2.6 Erase OperationPRELIMINARY PRELIMINARYPRELIMINARY 2.7 Recovering From Over-Erasure Flash-Write OperationPRELIMINARY PRELIMINARY 2.8 Reading From the Flash Array2.9 Protecting the Array PRELIMINARYPRELIMINARY Algorithm Implementations and Software ConsiderationsChapter PRELIMINARYHow the Algorithms Fit Into the Program-Erase-Reprogram Flow 3.1 How the Algorithms Fit Into the Program-Erase-Reprogram FlowPRELIMINARY PRELIMINARYHow the Algorithms Fit Into the Program-Erase-Reprogram Flow Figure 3±1. Algorithms in the Overall FlowPRELIMINARY PRELIMINARYPRELIMINARY 3.2 Programming or Clear AlgorithmFigure 3±2. The Programming Algorithm in the Overall Flow PRELIMINARYPRELIMINARY The main feature of the program/clear algorithm is the concept of program- ming an entire row of bits in a group. The F20x/F24x flash array is organized in rows of 32 words. That is, addresses 0000h through 001Fh are physically located on the same row of the flash memory array. The array is designed so that there is a dependence between the charge levels on adjacent even±odd addresses during programming. Programming the bits of an odd address re- duces the charge margin of the programmed bits the 0s in the preceding ad- jacent even address within the row. Similarly, programming the bits of an even address reduces the charge margin of the programmed bits in the next adjacent odd address within the row. Because of this dependence, if each address is programmed individually, the charge levels among programmed bits is not uniform. The programming algorithm improves the uniformity of charge levels on programmed bits by programming all of the words of a row in a group. For example, the contents of address 0000h is compared with the data to be programmed and one program pulse is applied if necessary. The same procedure is performed on addresses 0001h through 001Fh. The proce- dure repeats starting at address 0000h until no more program pulses are re- quired for any address in the row. The number of iterations of this loop equals the maximum number of program pulses required to program the bits in the rowPRELIMINARY Programming or Clear Algorithm Figure 3±3. Programming or Clear Algorithm FlowPRELIMINARY PRELIMINARYPRELIMINARY Power up the VCCP pinPRELIMINARY Programming or Clear Algorithm PRELIMINARYPRELIMINARY PRELIMINARY Before each program pulse is applied, a read of the byte is performed to deter- mine which bits have reached the programmed level. Any bits that have reached the programmed level are masked set to 1 in the WDATA register. This method of programming provides uniform charge levels among pro- grammed bits, whereas using a single, long program pulse could result in some bits having much more charge than others. The uniformity of charge lev- els among bits has the primary effect of reducing programming time and the secondary effect of reducing the time for a subsequent erase operation. To as- sure that the bits are programmed with enough margin, the reads associated with programming use the VER0 read modePRELIMINARY PRELIMINARY 3.3 Erase AlgorithmFigure 3±4. Erase Algorithm in the Overall Flow PRELIMINARYPRELIMINARY Table 3±2. Steps for Applying One Erase PulsePRELIMINARY PRELIMINARY 4 The actual address is restoredPRELIMINARY Erase Algorithm Figure 3±5. Erase Algorithm FlowPRELIMINARY PRELIMINARYPRELIMINARY 3.4 Flash-Write AlgorithmFigure 3±6. Flash-Write Algorithm in the Overall Flow PRELIMINARYPRELIMINARY Table 3±3. Steps for Applying One Flash-Write PulsePRELIMINARY Flash-Write Algorithm Figure 3±7. Flash-Write Algorithm FlowPRELIMINARY PRELIMINARYPRELIMINARY The CPU frequency range for the application is an important consideration for the depletion test, as well as for the program and erase operations. Because of the actual implementation of the flash memory circuitry, a bit in depletion mode is most easily detected at low frequency. Accordingly, if the application requires a variable CPU clock rate, the depletion test should be performed at the lowest frequency in the range. Only the read portion of the depletion test must be performed at the lower frequency, because it is the read that is used to detect depletion. The effective duration of the read operation can be ex- tended by sequentially executing multiple reads on the same location. Be- cause the same address is selected the entire time and internal control signals are maintained between reads, the final read is equivalent to a slow read. For example, if the DSP core is executing the programming algorithm at a CLKOUT rate of 20 MHz 50 ns, sequentially reading a location three times is equivalent to reading it once at 6.67 MHz 150 ns. The erase and flash-write algorithm implementations given in Appendix A use three reads to check for depletionPRELIMINARY PRELIMINARY PRELIMINARYPRELIMINARY Assembly Source Listings and Program ExamplesAppendixAppendixAA PRELIMINARYPRELIMINARY A.1 Assembly Source for AlgorithmsA.1.1 Header File for Constants and Variables, SVAR20.H PRELIMINARYPRELIMINARY Assembly Source for AlgorithmsAssembly Source Listings and Program Examples PRELIMINARYPRELIMINARY Assembly Source for AlgorithmsPRELIMINARY PRELIMINARY A.1.2 Clear Algorithm, SCLR20.ASMPRELIMINARY PRELIMINARY Assembly Source for AlgorithmsPRELIMINARY PRELIMINARY Assembly Source for AlgorithmsAssembly Source Listings and Program Examples PRELIMINARYPRELIMINARY Assembly Source for AlgorithmsPRELIMINARY PRELIMINARY Assembly Source for AlgorithmsAssembly Source Listings and Program Examples PRELIMINARYA-10 A.1.3 Erase Algorithm, SERA20.ASMPRELIMINARY PRELIMINARYPRELIMINARY Assembly Source for AlgorithmsAssembly Source Listings and Program Examples PRELIMINARYA-12 Assembly Source for AlgorithmsPRELIMINARY PRELIMINARYPRELIMINARY Assembly Source for AlgorithmsAssembly Source Listings and Program Examples PRELIMINARYA-14 Assembly Source for AlgorithmsPRELIMINARY PRELIMINARYPRELIMINARY A.1.4 Flash-Write Algorithm, SFLW20.ASMPRELIMINARY A-16 Assembly Source for AlgorithmsPRELIMINARY PRELIMINARYPRELIMINARY Assembly Source for AlgorithmsAssembly Source Listings and Program Examples PRELIMINARYA-18 Assembly Source for AlgorithmsPRELIMINARY PRELIMINARYPRELIMINARY A.1.5 Programming Algorithm, SPGM20.ASMPRELIMINARY A-20 Assembly Source for AlgorithmsPRELIMINARY PRELIMINARYPRELIMINARY Assembly Source for AlgorithmsAssembly Source Listings and Program Examples PRELIMINARYA-22 Assembly Source for AlgorithmsPRELIMINARY PRELIMINARYPRELIMINARY Assembly Source for AlgorithmsAssembly Source Listings and Program Examples PRELIMINARYA-24 Assembly Source for AlgorithmsPRELIMINARY PRELIMINARYPRELIMINARY A.1.6 Subroutines Used By All Four Algorithms, SUTILS20.ASMAssembly Source for Algorithms Assembly Source Listings and Program ExamplesA-26 Assembly Source for AlgorithmsPRELIMINARY PRELIMINARYPRELIMINARY A.2 C-Callable Interface to Flash AlgorithmsAssembly Source Listings and Program Examples PRELIMINARYA-28 PRELIMINARYPRELIMINARY C-Callable Interface to Flash AlgorithmsC-Callable Interface to Flash Algorithms Assembly Source Listings and Program ExamplesPRELIMINARY PRELIMINARYA-30 PRELIMINARYPRELIMINARY C-Callable Interface to Flash AlgorithmsC-Callable Interface to Flash Algorithms Assembly Source Listings and Program ExamplesPRELIMINARY PRELIMINARYPRELIMINARY A.3 Sample Assembly Code to Erase and Reprogram the TMS320F206A.3.1 Assembly Code for TMS320F206 PRELIMINARYPRELIMINARY PRELIMINARYA-34 PRELIMINARYPRELIMINARY PRELIMINARY Sample Assembly Code to Erase and Reprogram the TMS320F206Assembly Source Listings and Program Examples PRELIMINARYA-36 Sample Assembly Code to Erase and Reprogram the TMS320F206PRELIMINARY PRELIMINARYPRELIMINARY A.4 Sample C Code to Erase and Reprogram the TMS320F206PRELIMINARY Sample C Code to Erase and Reprogram the TMS320F206 A.4.2 Linker Command File for TMS320F206 Sample C CodePRELIMINARY PRELIMINARYSample C Code to Erase and Reprogram the TMS320F206 Assembly Source Listings and Program ExamplesPRELIMINARY PRELIMINARYPRELIMINARY A.5 Sample Assembly Code to Erase and Reprogram the TMS320F240A.5.1 Assembly Code for TMS320F240 PRELIMINARYPRELIMINARY Sample Assembly Code to Erase and Reprogram the TMS320F240Assembly Source Listings and Program Examples PRELIMINARYA-42 Sample Assembly Code to Erase and Reprogram the TMS320F240PRELIMINARY PRELIMINARYPRELIMINARY Sample Assembly Code to Erase and Reprogram the TMS320F240Assembly Source Listings and Program Examples PRELIMINARYA-44 Sample Assembly Code to Erase and Reprogram the TMS320F240PRELIMINARY PRELIMINARYPRELIMINARY A.5.2 Linker Command File for TMS320F240 Sample Assembly CodeSample Assembly Code to Erase and Reprogram the TMS320F240 Assembly Source Listings and Program ExamplesA-46 Sample Assembly Code to Erase and Reprogram the TMS320F240PRELIMINARY PRELIMINARYRev1.003/98 JGC A.6 Using the Algorithms With C Code to Erase and Reprogram the F240PRELIMINARY PRELIMINARYPRELIMINARY A.6.2 Linker Command File for TMS320F240 Sample C CodeUsing the Algorithms With C Code to Erase and Reprogram the F240 PRELIMINARYPRELIMINARY Using the Algorithms With C Code to Erase and Reprogram the F240Assembly Source Listings and Program Examples PRELIMINARYPRELIMINARY A.6.3 C Function for Disabling TMS320F240 Watchdog TimerUsing the Algorithms With C Code to Erase and Reprogram the F240 PRELIMINARYPRELIMINARY A.6.4 C Functions for Initializing the TMS320F240Using the Algorithms With C Code to Erase and Reprogram the F240 Assembly Source Listings and Program ExamplesA-52 Using the Algorithms With C Code to Erase and Reprogram the F240PRELIMINARY PRELIMINARYIndex IndexPRELIMINARY PRELIMINARYIndex PRELIMINARYPRELIMINARY Index PRELIMINARYPRELIMINARY Index PRELIMINARYPRELIMINARY