±5. Erase Algorithm Flow | Texas Instruments TMS320F20x/F24x DSP

PRELIMINARY

Erase Algorithm

Figure 3±5. Erase Algorithm Flow

	Start
	(all words=0000h)
	Set VER1
	bit in SEG_CTR
	Wait for
	td(BUSY-VERIFY)	Verify
		erase
	Read all locations
	using address
	complementing
	Clear all bits
	in SEG_CTR
	All	Yes
	words =	Yes
	words =
	FFFFh
	?	Set VER0 and
		Set VER0 and
	No	VER1 bits in
	No	SEG_CTR
		SEG_CTR
	Apply one
	erase pulse	Wait for
	to flash array	Wait for
	to flash array	td(BUSY-INVERSE)
	(see Table 3±2)	td(BUSY-INVERSE)
		Depletion
		Read first
	Erase	32 words
No	Erase
No	pulse count
	pulse count

≥Max² ?

					No	All
			Yes			32 words
						= 0000h?
	² See the device data sheet for						Yes
				Depletion
	the timing parameter values.	Device failure				Program array
				recovery

PRELIMINARY

Algorithm Implementations and Software Considerations

3-13

Image 47

Texas Instruments TMS320F20x/F24x DSP manual ±5. Erase Algorithm Flow

Contents

Literature Number SPRU282 September Important Notice Read This First Preliminary Related Documentation From Texas Instruments Preliminary If You Need Assistance Viii Contents Contents Figures Tables Introduction Basic Concepts of Flash Memory Technology ±1. TMS320 Devices With On-Chip Flash Eeprom TMS320F20x/F24x Flash Module ±1. TMS320F20x/F24x Program Space Memory Maps Benefits of Embedded Flash Memory in a DSP System Preliminary Topic Flash Operations and Control Registers Preliminary Flash Operations and Control Registers ±1. Flash Memory Logic Levels During Programming and Erasing Accessing the Flash Module 1 TMS320F206 Flash Access-Control Register ±2. Memory Maps in Register and Array Access Modes OUT 2 TMS320F24x Flash Access-Control Register Segment Control Register Segctr Flash Module Control Registers ±3. Segment Control Register Field Descriptions Write Address Register Wadrs Flash Test Register TST Write Data Register Wdata Read Modes Program Operation Erase Operation Recovering From Over-Erasure Flash-Write Operation Protecting the Array Reading From the Flash Array Algorithm Implementations Software Considerations How the Algorithms Fit Into the Program-Erase-Reprogram Flow ±1. Algorithms in the Overall Flow ±2. The Programming Algorithm in the Overall Flow Programming or Clear Algorithm Preliminary ±3. Programming or Clear Algorithm Flow Step Action Description Mask the data to program Preliminary ±4. Erase Algorithm in the Overall Flow Erase Algorithm ±2. Steps for Applying One Erase Pulse Preliminary ±5. Erase Algorithm Flow ±6. Flash-Write Algorithm in the Overall Flow Flash-Write Algorithm ±3. Steps for Applying One Flash-Write Pulse ±7. Flash-Write Algorithm Flow Preliminary Preliminary Assembly Source Listings Program Examples Header File for Constants and Variables, SVAR20.H Assembly Source for Algorithms BASE1 ErrorBASE0 BASE+0 Dloop ConstantsD5K D7K Protect Clear Algorithm, SCLR20.ASMSegst Segend AR1 Gclr PROTECT,SEGST,SEGEND DELAY,REGS,ARRAYSplk #0,ERROR AR0 Newrow Exit Splk #1,ERRORSacl Flst Lacl Fladrs Tblr Fldata Activate Write BIT Tblw SPAD1 Execute Command LARSET Delay Call DELAY,*,AR6 Wait Stop Write Operation Splk Shutdown Write Operation Tblw SPAD1 Execute Command LAR Bcnd PBDONE,EQ Tblw SPAD1 Execute Command LARPrgbyte Call SETRDVER0 Lacl BASE2 Erase Algorithm, SERA20.ASM Flash Write Command Word Erase Command WordErase Exebin Command Word Inverse Erase Command Word Xorerase Clrc OVMSacl Flend Call Setmode Nextivers Lacl BASE1 Splk #STOP,BASE0Inverase Splk #INVER,BASE0 Call Setmode Bldd Flash Stop command, and Ffff for Wdata Flash-Write Algorithm, SFLW20.ASM Bldd #FLST,BASE1 MaxflwFlws Flwrite Splk Call Array Access Flash Array DoneCall DELAY,*,AR6 Bcnd Setmode Call Lacl Tblw LAR Call Call RET LAR AR0,#MAXFLW Cmpr Programming Algorithm, SPGM20.ASM Gpgmj PROTECT,DELAY,REGS,ARRAYAR3 AR4 SUB Sacl BASE4 Setc Intm Globally Mask ALL Interrupts Splk #0,ERRORGpgmj Splk Mask ALL Interrupts Adjrow NEG Rowdone Lacl FladrsBcnd DONE, GT Lacl Fladrs Newrow SETRDVER0 Call Regs Access Flash Registers Shut Down Write Operation Tblw SPAD1 Execute Command LAR Pbend RET XOR FldataBcnd PBEND,EQ Subroutines Used By All Four Algorithms, SUTILS20.ASM Lacc Flst SUB OUT SPAD2,FACCESS0SPAD2,FACCESS1 OUT SPAD2,F24XACCS Callable Interface to Flash Algorithms PARMS+2 GclrSEGST,SEGEND,PROTECT PARMS+1 Arprotect Lacl ErrorErsparams Arstack 1PROTECT Sacl ErscountCall Flws LAR AR1,SVAR1 Call Gpgmj Popd *+ Assembly Code for TMS320F206 Sample Assembly Code to Erase and Reprogram the TMS320F206 PARMS+1 SUB Memory DLY Psaram Block B2Sections Psaram Sample C Code to Erase and Reprogram the TMS320F206 Linker Command File for TMS320F206 Sample C Code Block B2 Dsaram FLASH0FLASH1 BLKB2 Assembly Code for TMS320F240 Sample Assembly Code to Erase and Reprogram the TMS320F240 CKCR1 RticrWdcr CKCR0 LDP #PARMS Splk LDP #DPPF1PORRST, PLLRST, Illrst SWRST, Wdrst Lacl Syssr Accl = Syssr Sacl Syssr Daram LDP #PARMS B0PGM Linker Command File for TMS320F240 Sample Assembly CodeExtram Extram 0 /******Delay Subroutine Rev1.003/98 JGC Linker Command File for TMS320F240 Sample C Code B0DAT Block B2 Dsram Lacl Wdcr Function for Disabling TMS320F240 Watchdog TimerCompute Length Syscr Functions for Initializing the TMS320F240Sacl Wdcr Pshd Sacl Wdtcr Index Assembly code SERA2x.ASM Described 10 to Margin Role in single program pulse WRITE/ERASE field Described