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Texas Instruments TMS320F20x/F24x DSP manual Preliminary

Models: TMS320F20x/F24x DSP

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Error Call DELAY,*,AR6 Reset Register Command Word Accessing the Flash Module Tblw SPAD1 Execute Command LAR Assembly Source for Algorithms

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PRELIMINARY

3-18	PRELIMINARY

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Texas Instruments TMS320F20x/F24x DSP manual Preliminary

Page 51 Page 53

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Contents

Literature Number SPRU282 September Important Notice Read This First Preliminary Related Documentation From Texas Instruments Preliminary If You Need Assistance Viii Contents Contents Figures Tables Introduction Basic Concepts of Flash Memory Technology TMS320F20x/F24x Flash Module ±1. TMS320 Devices With On-Chip Flash Eeprom ±1. TMS320F20x/F24x Program Space Memory Maps Benefits of Embedded Flash Memory in a DSP System Preliminary Flash Operations and Control Registers Topic Preliminary Flash Operations and Control Registers ±1. Flash Memory Logic Levels During Programming and Erasing Accessing the Flash Module ±2. Memory Maps in Register and Array Access Modes 1 TMS320F206 Flash Access-Control Register 2 TMS320F24x Flash Access-Control Register OUT Flash Module Control Registers Segment Control Register Segctr ±3. Segment Control Register Field Descriptions Flash Test Register TST Write Address Register Wadrs Write Data Register Wdata Read Modes Program Operation Erase Operation Recovering From Over-Erasure Flash-Write Operation Reading From the Flash Array Protecting the Array Algorithm Implementations Software Considerations How the Algorithms Fit Into the Program-Erase-Reprogram Flow ±1. Algorithms in the Overall Flow Programming or Clear Algorithm ±2. The Programming Algorithm in the Overall Flow Preliminary ±3. Programming or Clear Algorithm Flow Step Action Description Mask the data to program Preliminary Erase Algorithm ±4. Erase Algorithm in the Overall Flow ±2. Steps for Applying One Erase Pulse Preliminary ±5. Erase Algorithm Flow Flash-Write Algorithm ±6. Flash-Write Algorithm in the Overall Flow ±3. Steps for Applying One Flash-Write Pulse ±7. Flash-Write Algorithm Flow Preliminary Preliminary Assembly Source Listings Program Examples Assembly Source for Algorithms Header File for Constants and Variables, SVAR20.H Error BASE0BASE+0 BASE1 Constants D5KD7K Dloop Clear Algorithm, SCLR20.ASM SegstSegend Protect Gclr PROTECT,SEGST,SEGEND DELAY,REGS,ARRAY Splk #0,ERRORAR0 AR1 Exit Splk #1,ERROR Sacl FlstLacl Fladrs Newrow Activate Write BIT Tblw SPAD1 Execute Command LAR SET Delay Call DELAY,*,AR6 Wait Stop Write Operation SplkShutdown Write Operation Tblw SPAD1 Execute Command LAR Tblr Fldata Tblw SPAD1 Execute Command LAR Prgbyte Call SETRDVER0Lacl BASE2 Bcnd PBDONE,EQ Erase Algorithm, SERA20.ASM Erase Command Word Erase Exebin Command WordInverse Erase Command Word Flash Write Command Word Clrc OVM Sacl FlendCall Setmode Xorerase Splk #STOP,BASE0 Inverase Splk #INVER,BASE0 Call SetmodeBldd Nextivers Lacl BASE1 Flash Stop command, and Ffff for Wdata Flash-Write Algorithm, SFLW20.ASM Flws MaxflwBldd #FLST,BASE1 Call Array Access Flash Array Done Call DELAY,*,AR6Bcnd Flwrite Splk LAR AR0,#MAXFLW Cmpr Setmode Call Lacl Tblw LAR Call Call RET Programming Algorithm, SPGM20.ASM PROTECT,DELAY,REGS,ARRAY AR3AR4 Gpgmj Setc Intm Globally Mask ALL Interrupts Splk #0,ERROR Gpgmj SplkMask ALL Interrupts SUB Sacl BASE4 Rowdone Lacl Fladrs Bcnd DONE, GTLacl Fladrs Newrow Adjrow NEG Shut Down Write Operation Tblw SPAD1 Execute Command LAR SETRDVER0 Call Regs Access Flash Registers Bcnd PBEND,EQ XOR FldataPbend RET Subroutines Used By All Four Algorithms, SUTILS20.ASM OUT SPAD2,FACCESS0 SPAD2,FACCESS1OUT SPAD2,F24XACCS Lacc Flst SUB Callable Interface to Flash Algorithms Gclr SEGST,SEGEND,PROTECTPARMS+1 PARMS+2 Lacl Error ErsparamsArstack Arprotect Sacl Erscount Call FlwsLAR AR1,SVAR1 1PROTECT Popd *+ Call Gpgmj Sample Assembly Code to Erase and Reprogram the TMS320F206 Assembly Code for TMS320F206 PARMS+1 SUB Memory Block B2 SectionsPsaram DLY Psaram Sample C Code to Erase and Reprogram the TMS320F206 Linker Command File for TMS320F206 Sample C Code FLASH0 FLASH1BLKB2 Block B2 Dsaram Sample Assembly Code to Erase and Reprogram the TMS320F240 Assembly Code for TMS320F240 Rticr WdcrCKCR0 CKCR1 LDP #DPPF1 PORRST, PLLRST, Illrst SWRST, Wdrst Lacl Syssr Accl = SyssrSacl Syssr LDP #PARMS Splk Daram LDP #PARMS Extram Linker Command File for TMS320F240 Sample Assembly CodeB0PGM Extram 0 /******Delay Subroutine Rev1.003/98 JGC Linker Command File for TMS320F240 Sample C Code Block B2 Dsram B0DAT Compute Length Function for Disabling TMS320F240 Watchdog TimerLacl Wdcr Functions for Initializing the TMS320F240 Sacl WdcrPshd Syscr Sacl Wdtcr Index Assembly code SERA2x.ASM Described 10 to Margin Role in single program pulse WRITE/ERASE field Described

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