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TMS320F20x/F24x DSP Embedded Flash Memory Technical Reference
Literature Number SPRU282 September
IMPORTANT NOTICE
About This Manual
How to Use This Manual
Read This First
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This document uses the following conventions
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Notational Conventions
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Related Documentation From Texas Instruments
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TMS320C2xx C Source Debugger Users Guide literature number SPRU151 tells you how to invoke the C2xx emulator and simulator ver- sions of the C source debugger interface. This book discusses various aspects of the debugger interface, including window management, com- mand entry, code execution, data management, and breakpoints. It also includes a tutorial that introduces basic debugger functionality
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2 Flash Operations and Control Registers
Contents
1 Introduction
A.1.1 Header File for Constants and Variables, SVAR20.H . . . . . . . . . . . . . . . . . . . . . A2 A.1.2 Clear Algorithm, SCLR20.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A5 A.1.3 Erase Algorithm, SERA20.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A10 A.1.4 Flash-Write Algorithm, SFLW20.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A15 A.1.5 Programming Algorithm, SPGM20.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A19 A.1.6 Subroutines Used By All Four Algorithms, SUTILS20.ASM . . . . . . . . . . . . . . . A25
Figures
2±2 Flash Module Control Registers
Tables
2±1 Operations that Modify the Contents of the Flash Array
1±1 TMS320 Devices With On-Chip Flash EEPROM
Topic
Introduction
Chapter
Page
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1.1 Basic Concepts of Flash Memory Technology
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1.2 TMS320F20x/F24x Flash Module
Table 1±1. TMS320 Devices With On-Chip Flash EEPROM
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TMS320F20x/F24x Flash Module
Figure 1±1. TMS320F20x/F24x Program Space Memory Maps
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1.3 Benefits of Embedded Flash Memory in a DSP System
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Chapter
Topic
Page
Flash Operations and Control Registers
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2.1 Operations that Modify the Contents of the F20x/F24x Flash Array
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This procedure is discussed in complete detail in Chapter
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Table 2±1. Operations that Modify the Contents of the Flash Array
Figure 2±1. Flash Memory Logic Levels During Programming and Erasing
Operations that Modify the Contents of the F20x/F24x Flash Array
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2.2 Accessing the Flash Module
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Figure 2±2. Memory Maps in Register and Array Access Modes
2.2.1 TMS320F206 Flash Access-Control Register
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2.2.2 TMS320F24x Flash Access-Control Register
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Figure 2±3. Segment Control Register SEGCTR
2.3 Flash Module Control Registers
Table 2±2. Flash Module Control Registers
2.3.1 Segment Control Register SEGCTR
Flash Module Control Registers
Table 2±3. Segment Control Register Field Descriptions
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Table 2±4. Flash Array Segments Summary
2.3.2 Flash Test Register TST
2.3.3 Write Address Register WADRS
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2.3.4 Write Data Register WDATA
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2.4 Read Modes
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2.5 Program Operation
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Erase Operation
2.6 Erase Operation
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2.7 Recovering From Over-Erasure Flash-Write Operation
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2.8 Reading From the Flash Array
2.9 Protecting the Array
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Algorithm Implementations and Software Considerations
Chapter
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How the Algorithms Fit Into the Program-Erase-Reprogram Flow
3.1 How the Algorithms Fit Into the Program-Erase-Reprogram Flow
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How the Algorithms Fit Into the Program-Erase-Reprogram Flow
Figure 3±1. Algorithms in the Overall Flow
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3.2 Programming or Clear Algorithm
Figure 3±2. The Programming Algorithm in the Overall Flow
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The main feature of the program/clear algorithm is the concept of program- ming an entire row of bits in a group. The F20x/F24x flash array is organized in rows of 32 words. That is, addresses 0000h through 001Fh are physically located on the same row of the flash memory array. The array is designed so that there is a dependence between the charge levels on adjacent even±odd addresses during programming. Programming the bits of an odd address re- duces the charge margin of the programmed bits the 0s in the preceding ad- jacent even address within the row. Similarly, programming the bits of an even address reduces the charge margin of the programmed bits in the next adjacent odd address within the row. Because of this dependence, if each address is programmed individually, the charge levels among programmed bits is not uniform. The programming algorithm improves the uniformity of charge levels on programmed bits by programming all of the words of a row in a group. For example, the contents of address 0000h is compared with the data to be programmed and one program pulse is applied if necessary. The same procedure is performed on addresses 0001h through 001Fh. The proce- dure repeats starting at address 0000h until no more program pulses are re- quired for any address in the row. The number of iterations of this loop equals the maximum number of program pulses required to program the bits in the row
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Programming or Clear Algorithm
Figure 3±3. Programming or Clear Algorithm Flow
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Power up the VCCP pin
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Programming or Clear Algorithm
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Before each program pulse is applied, a read of the byte is performed to deter- mine which bits have reached the programmed level. Any bits that have reached the programmed level are masked set to 1 in the WDATA register. This method of programming provides uniform charge levels among pro- grammed bits, whereas using a single, long program pulse could result in some bits having much more charge than others. The uniformity of charge lev- els among bits has the primary effect of reducing programming time and the secondary effect of reducing the time for a subsequent erase operation. To as- sure that the bits are programmed with enough margin, the reads associated with programming use the VER0 read mode
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3.3 Erase Algorithm
Figure 3±4. Erase Algorithm in the Overall Flow
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Table 3±2. Steps for Applying One Erase Pulse
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4 The actual address is restored
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Erase Algorithm
Figure 3±5. Erase Algorithm Flow
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3.4 Flash-Write Algorithm
Figure 3±6. Flash-Write Algorithm in the Overall Flow
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Table 3±3. Steps for Applying One Flash-Write Pulse
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Flash-Write Algorithm
Figure 3±7. Flash-Write Algorithm Flow
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The CPU frequency range for the application is an important consideration for the depletion test, as well as for the program and erase operations. Because of the actual implementation of the flash memory circuitry, a bit in depletion mode is most easily detected at low frequency. Accordingly, if the application requires a variable CPU clock rate, the depletion test should be performed at the lowest frequency in the range. Only the read portion of the depletion test must be performed at the lower frequency, because it is the read that is used to detect depletion. The effective duration of the read operation can be ex- tended by sequentially executing multiple reads on the same location. Be- cause the same address is selected the entire time and internal control signals are maintained between reads, the final read is equivalent to a slow read. For example, if the DSP core is executing the programming algorithm at a CLKOUT rate of 20 MHz 50 ns, sequentially reading a location three times is equivalent to reading it once at 6.67 MHz 150 ns. The erase and flash-write algorithm implementations given in Appendix A use three reads to check for depletion
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Assembly Source Listings and Program Examples
AppendixAppendixAA
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A.1 Assembly Source for Algorithms
A.1.1 Header File for Constants and Variables, SVAR20.H
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Assembly Source for Algorithms
Assembly Source Listings and Program Examples
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Assembly Source for Algorithms
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A.1.2 Clear Algorithm, SCLR20.ASM
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Assembly Source for Algorithms
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Assembly Source for Algorithms
Assembly Source Listings and Program Examples
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Assembly Source for Algorithms
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Assembly Source for Algorithms
Assembly Source Listings and Program Examples
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A-10
A.1.3 Erase Algorithm, SERA20.ASM
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Assembly Source for Algorithms
Assembly Source Listings and Program Examples
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A-12
Assembly Source for Algorithms
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Assembly Source for Algorithms
Assembly Source Listings and Program Examples
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A-14
Assembly Source for Algorithms
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A.1.4 Flash-Write Algorithm, SFLW20.ASM
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A-16
Assembly Source for Algorithms
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Assembly Source for Algorithms
Assembly Source Listings and Program Examples
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A-18
Assembly Source for Algorithms
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A.1.5 Programming Algorithm, SPGM20.ASM
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A-20
Assembly Source for Algorithms
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Assembly Source for Algorithms
Assembly Source Listings and Program Examples
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A-22
Assembly Source for Algorithms
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Assembly Source for Algorithms
Assembly Source Listings and Program Examples
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A-24
Assembly Source for Algorithms
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A.1.6 Subroutines Used By All Four Algorithms, SUTILS20.ASM
Assembly Source for Algorithms
Assembly Source Listings and Program Examples
A-26
Assembly Source for Algorithms
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A.2 C-Callable Interface to Flash Algorithms
Assembly Source Listings and Program Examples
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A-28
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C-Callable Interface to Flash Algorithms
C-Callable Interface to Flash Algorithms
Assembly Source Listings and Program Examples
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A-30
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C-Callable Interface to Flash Algorithms
C-Callable Interface to Flash Algorithms
Assembly Source Listings and Program Examples
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A.3 Sample Assembly Code to Erase and Reprogram the TMS320F206
A.3.1 Assembly Code for TMS320F206
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A-34
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Sample Assembly Code to Erase and Reprogram the TMS320F206
Assembly Source Listings and Program Examples
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A-36
Sample Assembly Code to Erase and Reprogram the TMS320F206
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A.4 Sample C Code to Erase and Reprogram the TMS320F206
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Sample C Code to Erase and Reprogram the TMS320F206
A.4.2 Linker Command File for TMS320F206 Sample C Code
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Sample C Code to Erase and Reprogram the TMS320F206
Assembly Source Listings and Program Examples
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A.5 Sample Assembly Code to Erase and Reprogram the TMS320F240
A.5.1 Assembly Code for TMS320F240
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Sample Assembly Code to Erase and Reprogram the TMS320F240
Assembly Source Listings and Program Examples
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A-42
Sample Assembly Code to Erase and Reprogram the TMS320F240
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Sample Assembly Code to Erase and Reprogram the TMS320F240
Assembly Source Listings and Program Examples
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A-44
Sample Assembly Code to Erase and Reprogram the TMS320F240
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A.5.2 Linker Command File for TMS320F240 Sample Assembly Code
Sample Assembly Code to Erase and Reprogram the TMS320F240
Assembly Source Listings and Program Examples
A-46
Sample Assembly Code to Erase and Reprogram the TMS320F240
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Rev1.003/98 JGC
A.6 Using the Algorithms With C Code to Erase and Reprogram the F240
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A.6.2 Linker Command File for TMS320F240 Sample C Code
Using the Algorithms With C Code to Erase and Reprogram the F240
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Using the Algorithms With C Code to Erase and Reprogram the F240
Assembly Source Listings and Program Examples
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A.6.3 C Function for Disabling TMS320F240 Watchdog Timer
Using the Algorithms With C Code to Erase and Reprogram the F240
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A.6.4 C Functions for Initializing the TMS320F240
Using the Algorithms With C Code to Erase and Reprogram the F240
Assembly Source Listings and Program Examples
A-52
Using the Algorithms With C Code to Erase and Reprogram the F240
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Index
Index
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Index
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Index
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Index
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