Texas Instruments TMS320F20x/F24x DSP manual Preliminary, Index

Models: TMS320F20x/F24x DSP

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Index

PRELIMINARY

erase algorithm

 

 

 

 

 

 

 

assembly code (SERA2x.ASM)

A-10

described

3-10 to 3-13

 

 

 

 

flow diagram

3-13

 

 

 

 

in overall flow

3-10

 

 

 

 

erase() function (C code listing)

A-27

 

erase operation

 

 

 

 

 

 

 

described

2-14

 

 

 

 

 

following flash±write operation

2-15

frequency range

3-12

 

 

 

 

logic levels

2-4

 

 

 

 

 

role of WDATA

2-11

 

 

 

 

VER1 read mode

2-12

 

 

 

 

verification of erased bits

2-12

 

 

worst±case voltage for reading erased cell 2-12

erase protection

 

3-11

 

 

 

 

erase pulse

2-14

 

 

 

 

 

 

example for TMS320F206

 

 

 

 

assembly code

 

A-32, A-40

 

 

 

C code that calls flash.asm

 

A-37, A-47

linker command file A-35, A-38, A-45, A-48

execute bit (EXE)

 

 

 

 

 

 

described

2-9

 

 

 

 

 

 

in mechanism for array protection

2-16

location in SEG_CTR register

2-8

 

relation to erase pulse 2-14

 

 

 

relation to flash±write pulse

2-15, 3-14

relation to program pulse

2-13

 

 

role in single erase pulse

3-11

 

 

role in single flash±write pulse

3-15

role in single program pulse

3-9

 

execute key bits (KEY1, KEY0)

 

 

 

described

2-9

 

 

 

 

 

 

in mechanism for array protection

2-16

location in SEG_CTR register

2-8

 

role in single erase pulse

3-11

 

 

role in single flash±write pulse

3-15

role in single program pulse

3-9

 

extending a read

3-5, 3-17

 

 

 

 

F

flash memory size 1-3 flash module 1-3

flash operation (block operation) 1-2

flash±write algorithm

assembly code (SFLW2x.ASM) A-15

described

3-14

flow diagram

3-16

in overall flow

3-14

flash±write operation

described

1-2, 2-15

similarity to erase 2-15

flash±write pulse

2-15, 3-14

frequency range

 

erasing 3-12

 

flash±write

3-17

programming

3-5

G

global parameters in the calling code A-2

H

header file for constants and variables (SVAR2x.H) A-2

I

IN instruction 2-7

inverse±erase read mode 2-12, 2-15, 3-15

K

KEY1, KEY0 bits described 2-9

in mechanism for array protection 2-16

location in SEG_CTR register

2-8

role in single erase pulse 3-11

 

role in single flash±write pulse

3-15

role in single program pulse 3-9

L

limited number of bits programmed at one time 2-13

linker command files

 

 

for TMS320F206 sample assembly code

A-35

for TMS320F206 sample C code

A-38

 

for TMS320F240 sample assembly code

A-45

for TMS320F240 sample C code

A-48

 

Index-2

PRELIMINARY

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Texas Instruments TMS320F20x/F24x DSP manual Preliminary, Index