Intel STL2 manual

Contents

Main Revision History Disclaimers Table of Contents Page Page List of Figures List of Tables Page 1. Introduction 1.1 Purpose 1.2 Audience 1.3 STL2 Server Board Feature Overview 1.4 STL2 Server Board Block Diagram STL2 Server Board TPS Introduction Revision 1.0 1-3 NB6635 North Bridge 3.0 LE IB6566 South Bridge Figure 1-1. STL2 Server Board Block Diagram STL2 Server Board Block Diagram 133 MHz System Bus Page 2. STL2 Server Board Architecture Overview 2.1 Intel Pentium III Processor Subsystem 2.1.1 Supported Processor Types 2.1.2 Dual Processor Operation 2.1.3 PGA370 Socket 2.1.4 Processor Bus Termination / Regulation / Power 2.1.5 Termination Package 2.1.6 APIC Bus 2.2 ServerWorks ServerSet III LE Chipset 2.3 Memory Note: 2.4 PCI I/O Subsystem 2.4.1 64-bit / 66 MHz PCI Subsystem Revision 1.0 2-9 Table 2-2. SCSI Transfer Speeds Table 2-3. Embedded SCSI Supported PCI Commands 2.4.2 32-bit/33 MHz PCI Subsystem Page Page Revision 1.0 2-13 2.4.2.2.2 Video Controller PCI Commands The Rage IIC supports the following PCI commands: Table 2-4. Video Controller Supported PCI Commands Table 2-5. Standard VGA Modes Page 2.5 Chipset Support Components 2.5.1 Legacy I/O (Super I/O) National* PC97317VUL Page 2.5.2 BIOS Flash 2.5.3 External Device Connectors 2.6 Interrupt Routing 2.6.1 Default I/O APIC 2.6.2 Extended I/O APIC STL2 Server Board Architecture Overview STL2 Server Board TPS 2-18 PIC IB6566 South Bridge Figure 2-3. STL2 Baseboard Interrupt Routing Diagram (PIC mode) PCI Interrupt Router Revision 1.0 2-19 Figure 2-4. STL2 Baseboard Interrupt Routing Diagram (Symmetric mode) 2-20 2.6.3 PCI Ids The STL2 server board PCI Ids are defined as follows: Table 2-6. STL2 PCI IDs 2.6.4 Relationship between PCI IRQ and PCI Device The relationship between PCI IRQ and PCI devices are defined as follows on the STL2 server board: Page Page 3. Server Management 3.1 Baseboard Management Controller 3-24 fornt panel lock/unlock initiation 3.2 Hardware Sensors The following table lists the hardware sensors present on the STL2 server board. Revision 1.0 3-25 3-26 Revision 1.0 3-27 3.3 ACPI maintain coherency. 3.4 AC Link Mode 3.5 Wake On LAN Function 4. Basic Input Output System (BIOS) 4.1 BIOS Overview 4.1.1 System BIOS 4.1.2 Flash Update Utility 4.2 Setup Utility 4.2.1 Configuration Utilities Overview 4.2.2 Setup Utility Operation Page Page 4-34 Table 4-2. Main Menu Selections Revision 1.0 4-35 Table 4-3. Primary Master and Slave Adapters Submenu Selections Table 4-4. Processor Settings Submenu Selections 4-36 Table 4-5. Advanced Menu Selections Table 4-6. Memory Reconfiruation Submenu Selections Revision 1.0 4-37 Table 4-7. Peripheral Configuration Submenu Selections 4-38 Table 4-8. PCI Device Submenu Selections Table 4-9. Option ROM Submenu Selections Table 4-10. Numlock Submenu Selections Revision 1.0 4-39 4.2.2.6 Security Menu Selections Table 4-11. Security Menu Selections 4-40 Table 4-12. Secure Mode Submenu Selections 4.2.2.7 System Hardware Menu Selections Table 4-13. Server Menu Selections Table 4-14. Wake On Events Submenu Selections Revision 1.0 4-41 Table 4-15. Console Redirection Submenu Selections Table 4-16. Boot Menu Selections Table 4-17. Boot Device Priority Selections 4-42 4.3 CMOS Memory Definition 4.4 CMOS Default Override 4.5 Flash Update Utility 4.5.1 Loading the System BIOS 4.5.2 OEM Customization Page 4-46 The following code fragment shows the header and format for a user binary: Table 4-21. User Binary Area Scan Point Definitions 4.5.3 Language Area 4.5.4 Recovery Mode 4.6 Error Messages and Error Codes 4.6.1 POST Codes Revision 1.0 4-49 Table 4-24. Standard BIOS Port-80 Codes 4-50 Revision 1.0 4-51 4-52 Table 4-25. Recovery BIOS Port-80 Codes 4.6.2 POST Error Codes and Messages Table 4-26. POST Error Messages and Codes Revision 1.0 4-53 4-54 4.7 Identifying BIOS and BMC Revision Levels 4.7.1 BIOS Revision Level Identification 4.7.2 BMC Revision Level Identification 4.8 Adaptec SCSI Utility 4.8.1 Running the SCSI Utility 4.8.2 Adaptec SCSI Utility Configuration Settings Revision 1.0 4-57 Table 4-27. Adaptec SCSI Utility Setup Configurations Page Page Page 5. Jumpers and Connectors 5-62 The following diagram shows the location of the connectors on the STL2 server board I/O panel. Figure 5-2. I/O Back Panel Connectors I/O Back Panel location key for Figure 5-1: 5.1 Jumper Blocks 5.1.1 Setting CMOS/Password Clear Jumper Block 1J15 Page Page 5.1.2 Setting Configuration Jumper Block 1L4 Revision 1.0 5-67 Table 5-4. Jumper Block 1L4 Settings 5.1.3 Setting Configuration Jumper Block 6A This section provides pin information about the connectors on the STL2 server board. 5.2 Connectors 5-68 5.2.1 Main ATX Power Connector (P33) Table 5-6. Main ATX Power Connector Pinout 5.2.2 Auxilary ATX Power Connector (P34) Table 5-7. Auxiliary ATX Power Connector Pinout 5.2.3 I2C Power Connector (P37) 5.2.4 System Fan Connectors (P29, P27, P11) 5.2.5 Processor Connectors (P12, P36) 5.2.6 Speaker Connector (P31) 5.2.7 Speaker Connector (P25) 5-70 5.2.8 Diskette Drive Connector (P20) Figure 5-3. Diskette Drive Connector Pin Diagram Table 5-13. Diskette Drive Connector Pinout 5.2.9 SVGA Video Port Table 5-14. Video Port Connector Pinout Revision 1.0 5-71 5.2.10 Keyboard and Mouse Connectors The keyboard and mouse connectors are functionally equivalent. Table 5-15. Keyboard and Mouse Connector Pinouts 5.2.11 Parallel Port Table 5-16. Parallel Port Connector Pinouts 5.2.13 RJ-45 LAN Connector Table 5-18. RJ-45 LAN Connector Signals 5.2.14 USB Connectors Table 5-19. USB Connectors Revision 1.0 5-73 5.2.15 Ultra SCSI Connector (P9) Table 5-20. Ultra SCSI Connector Pinout 5.2.16 Ultra160 SCSI Connector (P8) Table 5-21. Ultra160 SCSI Connector 5-74 5.2.17 IDE Connector (P19) Figure 5-4. IDE Connector Pin Diagram Table 5-22. IDE Connector Pinout Revision 1.0 5-75 5.2.18 32-Bit PCI Connector Table 5-23. 32-Bit PCI Connector Pinout 5-76 5.2.19 64-Bit PCI Connector Table 5-24. 64-Bit PCI Connctor Pinout Revision 1.0 5-77 5.2.20 Front Panel 24-pin Connector Pinout (P23) Table 5-25. Front Panel 24-pin Connector Pinout 5-78 Page Page 6. Power Consumption 6.1 Calculated Power Consumption 6.2 Measured Power Consumption Page Page 8. Regulatory and Integration Information 8.1 Regulatory Compliance 8.2 Installation Instructions 8.2.1 Ensure EMC 8.2.2 Ensure Host Computer and Accessory Module Certifications 8.2.3 Prevent Power Supply Overload 8.2.4 Place Battery Marking on Computer WARNING: 8.2.5 Use Only for Intended Applications 8.2.6 Installation Precautions 8.3 Environmental Limits 8.3.1 System Office Environment 8.3.2 System Environmental Testing Page Revision 1.0 I Glossary Reference Documents Revision 1.0 III Index A B C D J L M N P T U V W Z