Intel STL2 manual 2.2ServerWorks ServerSet III LE Chipset, 2.3Memory, ∙NB6635 North Bridge 3.0LE

STL2 Server Board TPS STL2 Server Board Architecture Overview

The boxed processor fan heatsink will keep the processor core at the recommended junction temperature, as long as airflow through the fan heatsink is unimpeded. It is recommended that the air temperature entering the fan inlet be below 45°C (measured at 0.3 inches above the fan hub).

2.2ServerWorks ServerSet III LE Chipset

The ServerWorks ServerSet III LE chipset provides an integrated I/O bridge and memory controller and a flexible I/O subsystem core (PCI), targeted for multiprocessor systems and standard high-volume servers that are based on the Intel Pentium III processor. The ServerWorks ServerSet III LE chipset consists of two components:

∙NB6635 North Bridge 3.0LE

The NB6635 North Bridge 3.0LE is responsible for accepting access requests from the host (processor) bus and for directing those accesses to memory or to one of the PCI buses. The NB6635 North Bridge 3.0LE monitors the host bus, examining addresses for each request. Accesses may be directed to a memory request queue for subsequent forwarding to the memory subsystem, or to an outbound request queue for subsequent forwarding to one of the PCI buses. The NB6635 North Bridge 3.0LE is reponsible for controlling data transfers to and from the memory. The NB6635 North Bridge 3.0LE provides the interface for both the 64-bit/66 MHz, Revision 2.2-compliant PCI bus and the 32-bit/33 MHz, Revision 2.2-compliant PCI bus. The NB6635 North Bridge 3.0LE is both a master and target on both PCI buses.

∙IB6566 South Bridge

The IB6566 South Bridge controller has several components. It can be both a master and a target on the 32-bit/33 MHz PCI bus. The IB6566 South Bridge also includes a USB controller and an IDE controller. The IB6566 South Bridge is responsible for many of the power management functions, with ACPI control registers built in. The IB6566 South Bridge provides a number of GPIO pins.

2.3Memory

The STL2 server board contains four 168-pin DIMM sockets. Memory is partitioned as four banks of registered SDRAM DIMMs, each of which provides 72 bits of noninterleaved memory (64-bit main memory plus ECC).

The STL2 server board supports up to four 3.3V, registered ECC SDRAM DIMMs that are compliant with the JEDEC PC133 specification. A wide range of DIMM sizes are supported, including 64 MB, 128 MB, 256 MB, 512 MB, and 1GB DIMMs. The minimum supported memory configuration is 64 MB using one DIMM. The maximum configurable memory size is 4 GB using four DIMMs.

Note: Neither PC100 DIMMs nor non-ECC DIMMs can be used.

DIMMs may be installed in one, two, three, or four DIMM slots and must be populated starting with the lowest numbered slot and filling the slots in consecutive order. Empty memory slots between DIMMs are not supported. Although the STL2 server board architecture allows the user to mix various sizes of DIMMS, Intel recommends that module and DRAM vendors not be mixed in the same server system.

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