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Intel STL2 manual < This page intentionally left blank >, Revision, 4-59

Models: STL2

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STL2 Server Board TPS

Basic Input Output System (BIOS)

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Page 67

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Intel STL2 manual < This page intentionally left blank >, Revision, 4-59

Contents

Technical Product Specification Revision September 22, Enterprise Platforms GroupSTL2 Server Board STL2 Server Board TPS Revision HistoryDisclaimers Revision HistoryServer Management Table of ContentsIntroduction 2. STL2 Server Board Architecture Overview5-61 4. Basic Input Output System BIOS5. Jumpers and Connectors 4-297-83 Power ConsumptionMechanical Specifications 6-81List of Figures List of Tables Table 4-26.POST Error Messages and Codes 1.2Audience 1.3STL2 Server Board Feature Overview1.Introduction 1.1Purpose1.4STL2 Server Board Block Diagram BIOS STL2 Server Board Block DiagramFigure 1-1.STL2 Server Board Block Diagram ServerSet 3.0 LE STL2 FeaturesIntroduction < This page intentionally left blank >STL2 Server Board TPS 2.1 Intel Pentium III Processor Subsystem 2.STL2 Server Board Architecture Overview2.1.1Supported Processor Types 2.1.6APIC Bus 2.1.2Dual Processor Operation2.1.3PGA370 Socket 2.1.5Termination Package∙IB6566 South Bridge 2.2ServerWorks ServerSet III LE Chipset2.3Memory ∙NB6635 North Bridge 3.0LE2.4.164-bit /66 MHz PCI Subsystem 2.4PCI I/O Subsystem2.4.1.1Ultra160 / Ultra WideSCSI Controller Revision 2.4.1.1.1AIC-7899Supported PCI Commands2.4.1.1.2SCSI Bus 2.4.232-bit/33MHz PCI Subsystem2.4.2.1Network Interface Controller NIC 2.4.2.1.1Supported Network Features 2.4.2.2Video Controller 2.4.2.2.1Video Controller PCI SignalsTable 2-5.Standard VGA Modes 2.4.2.2.2Video Controller PCI Commands2.4.2.2.3Video Modes Table 2-4.Video Controller Supported PCI Commands2.4.2.3.1PCI Interface 2.4.2.3IB6566 South Bridge2.4.2.3.2PCI Bus Master IDE Interface 2.4.2.3.3USB Interface 2.4.2.6Power Management2.5Chipset Support Components 2.5.1Legacy I/O Super I/O National* PC97317VUL2.5.1.2Parallel Port 2.5.1.4Keyboard and Mouse Connectors2.5.1.7Power Management Controller 2.5.1.1Serial Ports2.6Interrupt Routing 2.5.2BIOS Flash2.5.3External Device Connectors 2.6.1Default I/O APICRouter 2-18South Interrupt2-19 Revision2.6.4Relationship between PCI IRQ and PCI Device 2.6.3PCI IdsTable 2-6.STL2 PCI IDs STL2 Server Board Architecture Overview Revision2-21 STL2 Server Board TPSPage 3.1Baseboard Management Controller 3.Server Management3-24 3.2Hardware Sensors∙Monitors the event receiver ∙Controls Wake-on-Lanvia Magic Packet* support3-25 RevisionPlatform Security 3-263.3ACPI 3.5Wake On LAN Function 3.4AC Link Mode4.1BIOS Overview 4.Basic Input Output System BIOS4.1.2Flash Update Utility 4.1.1System BIOS4.1.2.1System Flash ROM Layout 4.2.1Configuration Utilities Overview 4.2Setup Utility4.2.2Setup Utility Operation F1 Help 4.2.2.1Entering Setup Utility4.2.2.2Keyboard Command Bar Enter Execute CommandF6/+ Change Value F9 Setup Defaults←→ Select Menu F5/– Change ValueTable 4-2.Main Menu Selections 4.2.2.4Main Menu Selections∙System Menu ∙Boot Menu ∙Exit Menu These and associated submenus are described belowRevision Table 4-4.Processor Settings Submenu Selections4-35 Table 4-5.Advanced Menu Selections 4.2.2.5Advanced Menu Selections4-36 4-37 Revision4-38 Table 4-8.PCI Device Submenu SelectionsTable 4-9.Option ROM Submenu Selections Table 4-10.Numlock Submenu Selections4-39 4.2.2.6Security Menu SelectionsTable 4-11.Security Menu Selections RevisionTable 4-14.Wake On Events Submenu Selections 4.2.2.7System Hardware Menu SelectionsTable 4-12.Secure Mode Submenu Selections Table 4-13.Server Menu SelectionsTable 4-15.Console Redirection Submenu Selections 4.2.2.8Boot Menu SelectionsTable 4-16.Boot Menu Selections Table 4-17.Boot Device Priority Selections4.2.2.9Exit Menu Selections 4.3CMOS Memory Definition4.5Flash Update Utility 4.4CMOS Default Override4.5.1Loading the System BIOS 4.5.2OEM Customization 4.5.2.1User-suppliedBIOS Code SupportBit offset from start of CMOS of first bit Revision4-45 # of bit available –1Scan Point 4.5.2.2Scan Point DefinitionsBasic Input Output System BIOS STL2 Server Board TPS4.5.3Language Area 4.5.4Recovery Mode4.5.2.3OEM Splash Screen 4.6.1POST Codes 4.6Error Messages and Error CodesCheckpoint 04Bh will be broken down to Table 4-24.Standard BIOS Port-80Codes∙Each group is made one-based1 through Example4-50 Configure advanced chipset registers4-51 Revision4-52 4.6.2POST Error Codes and MessagesTable 4-25.Recovery BIOS Port-80Codes Table 4-26.POST Error Messages and Codes4-53 Revision4-54 Basic Input Output System BIOSError Message Error4.7.1BIOS Revision Level Identification 4.7Identifying BIOS and BMC Revision Levels4.7.2BMC Revision Level Identification 4.8Adaptec SCSI Utility 4.8.2Adaptec SCSI Utility Configuration Settings4.8.1Running the SCSI Utility Revision Basic Input Output System BIOSRecommended Setting or User Setting4-58 4.8.3Exiting Adaptec SCSI UtilityRevision < This page intentionally left blank >4-59 Page 5-61 5.Jumpers and ConnectorsJumper and connector location key for Figure RevisionFigure 5-2.I/O Back Panel Connectors I/O Back Panel location key for Figure5-62 5.1Jumper Blocks 5.1.1.2Clearing CMOS 5.1.1.1Clearing and Changing a PasswordRevision 5.1.1.3Perfoming a BIOS Recovery Boot5-65 5.1.2Setting Configuration Jumper Block 1L4 5.1.3Setting Configuration Jumper Block 6A 5.2ConnectorsTable 5-6.Main ATX Power Connector Pinout 5.2.1Main ATX Power Connector P335.2.2Auxilary ATX Power Connector P34 5.2.3I2C Power Connector P375.2.7Speaker Connector P25 5.2.4System Fan Connectors P29, P27, P115.2.5Processor Connectors P12, P36 5.2.6Speaker Connector P31Table 5-13.Diskette Drive Connector Pinout 5.2.8Diskette Drive Connector P205.2.9SVGA Video Port Figure 5-3.Diskette Drive Connector Pin DiagramTable 5-15.Keyboard and Mouse Connector Pinouts 5.2.10Keyboard and Mouse Connectors5.2.11Parallel Port 5.2.12Serial Ports COM1 and COM2Table 5-19.USB Connectors 5.2.13RJ-45LAN Connector5.2.14USB Connectors Table 5-18. RJ-45LAN Connector SignalsTable 5-21.Ultra160 SCSI Connector 5.2.15Ultra SCSI Connector P95.2.16Ultra160 SCSI Connector P8 Table 5-20.Ultra SCSI Connector Pinout5-74 5.2.17IDE Connector P19Figure 5-4.IDE Connector Pin Diagram Table 5-22.IDE Connector Pinout5-75 5.2.1832-BitPCI ConnectorTable 5-23. 32-BitPCI Connector Pinout RevisionTable 5-24. 64-BitPCI Connctor Pinout 5.2.1964-BitPCI Connector5-76 5-77 5.2.20Front Panel 24-pinConnector Pinout P23Table 5-25.Front Panel 24-pinConnector Pinout RevisionReserved 5-78Revision < This page intentionally left blank >5-79 Page 6.1Calculated Power Consumption 6.Power ConsumptionDevices 6.2Measured Power ConsumptionPower Consumption STL2 Server Board TPSRevision 7.Mechanical Specifications7-83 STL2 Server Board TPS Mechanical Specifications< This page intentionally left blank > 7-848.1Regulatory Compliance 8.Regulatory and Integration Information8.2.1Ensure EMC 8.2Installation Instructions8.2.2.2In the United States 8.2.3Prevent Power Supply Overload8.2.4Place Battery Marking on Computer 8.2.2.1In Europe8.3.1System Office Environment 8.2.6Installation Precautions8.3Environmental Limits 8.2.5Use Only for Intended Applications∙Shock Packaged and Unpackaged 8.3.2System Environmental Testing∙Temperature Operating and Non-Operating ∙Humidity Non-OperatingSTL2 Server Board TPS < This page intentionally left blank >8-90 Regulatory and Integration InformationRevision GlossaryReference Documents Revision IndexSee POST, 3-22, 3-24, 3-25, 4-29,4- 30, 4-33, Revision