STL2 Server Board
Revision September 22, Enterprise Platforms Group
Technical Product Specification
Revision History
Revision History
Disclaimers
STL2 Server Board TPS
2. STL2 Server Board Architecture Overview
Table of Contents
Introduction
Server Management
4-29
4. Basic Input Output System BIOS
5. Jumpers and Connectors
5-61
6-81
Power Consumption
Mechanical Specifications
7-83
List of Figures
List of Tables
Table 4-26.POST Error Messages and Codes
1.1Purpose
1.3STL2 Server Board Feature Overview
1.Introduction
1.2Audience
1.4STL2 Server Board Block Diagram
ServerSet 3.0 LE STL2 Features
STL2 Server Board Block Diagram
Figure 1-1.STL2 Server Board Block Diagram
BIOS
STL2 Server Board TPS
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Introduction
2.1.1Supported Processor Types
2.STL2 Server Board Architecture Overview
2.1 Intel Pentium III Processor Subsystem
2.1.5Termination Package
2.1.2Dual Processor Operation
2.1.3PGA370 Socket
2.1.6APIC Bus
∙NB6635 North Bridge 3.0LE
2.2ServerWorks ServerSet III LE Chipset
2.3Memory
∙IB6566 South Bridge
2.4.1.1Ultra160 / Ultra WideSCSI Controller
2.4PCI I/O Subsystem
2.4.164-bit /66 MHz PCI Subsystem
2.4.1.1.1AIC-7899Supported PCI Commands
Revision
2.4.2.1Network Interface Controller NIC
2.4.232-bit/33MHz PCI Subsystem
2.4.1.1.2SCSI Bus
2.4.2.1.1Supported Network Features
2.4.2.2.1Video Controller PCI Signals
2.4.2.2Video Controller
Table 2-4.Video Controller Supported PCI Commands
2.4.2.2.2Video Controller PCI Commands
2.4.2.2.3Video Modes
Table 2-5.Standard VGA Modes
2.4.2.3.2PCI Bus Master IDE Interface
2.4.2.3IB6566 South Bridge
2.4.2.3.1PCI Interface
2.5.1Legacy I/O Super I/O National* PC97317VUL
2.4.2.6Power Management
2.5Chipset Support Components
2.4.2.3.3USB Interface
2.5.1.1Serial Ports
2.5.1.4Keyboard and Mouse Connectors
2.5.1.7Power Management Controller
2.5.1.2Parallel Port
2.6.1Default I/O APIC
2.5.2BIOS Flash
2.5.3External Device Connectors
2.6Interrupt Routing
Interrupt
2-18
South
Router
Revision
2-19
Table 2-6.STL2 PCI IDs
2.6.3PCI Ids
2.6.4Relationship between PCI IRQ and PCI Device
STL2 Server Board TPS
Revision
2-21
STL2 Server Board Architecture Overview
Page
3.Server Management
3.1Baseboard Management Controller
∙Controls Wake-on-Lanvia Magic Packet* support
3.2Hardware Sensors
∙Monitors the event receiver
3-24
Revision
3-25
3-26
Platform Security
3.3ACPI
3.4AC Link Mode
3.5Wake On LAN Function
4.Basic Input Output System BIOS
4.1BIOS Overview
4.1.2.1System Flash ROM Layout
4.1.1System BIOS
4.1.2Flash Update Utility
4.2.2Setup Utility Operation
4.2Setup Utility
4.2.1Configuration Utilities Overview
Enter Execute Command
4.2.2.1Entering Setup Utility
4.2.2.2Keyboard Command Bar
F1 Help
F5/– Change Value
F9 Setup Defaults
←→ Select Menu
F6/+ Change Value
These and associated submenus are described below
4.2.2.4Main Menu Selections
∙System Menu ∙Boot Menu ∙Exit Menu
Table 4-2.Main Menu Selections
4-35
Table 4-4.Processor Settings Submenu Selections
Revision
4-36
4.2.2.5Advanced Menu Selections
Table 4-5.Advanced Menu Selections
Revision
4-37
Table 4-10.Numlock Submenu Selections
Table 4-8.PCI Device Submenu Selections
Table 4-9.Option ROM Submenu Selections
4-38
Revision
4.2.2.6Security Menu Selections
Table 4-11.Security Menu Selections
4-39
Table 4-13.Server Menu Selections
4.2.2.7System Hardware Menu Selections
Table 4-12.Secure Mode Submenu Selections
Table 4-14.Wake On Events Submenu Selections
Table 4-17.Boot Device Priority Selections
4.2.2.8Boot Menu Selections
Table 4-16.Boot Menu Selections
Table 4-15.Console Redirection Submenu Selections
4.3CMOS Memory Definition
4.2.2.9Exit Menu Selections
4.5.1Loading the System BIOS
4.4CMOS Default Override
4.5Flash Update Utility
4.5.2.1User-suppliedBIOS Code Support
4.5.2OEM Customization
# of bit available –1
Revision
4-45
Bit offset from start of CMOS of first bit
STL2 Server Board TPS
4.5.2.2Scan Point Definitions
Basic Input Output System BIOS
Scan Point
4.5.2.3OEM Splash Screen
4.5.4Recovery Mode
4.5.3Language Area
4.6Error Messages and Error Codes
4.6.1POST Codes
Example
Table 4-24.Standard BIOS Port-80Codes
∙Each group is made one-based1 through
Checkpoint 04Bh will be broken down to
Configure advanced chipset registers
4-50
Revision
4-51
Table 4-26.POST Error Messages and Codes
4.6.2POST Error Codes and Messages
Table 4-25.Recovery BIOS Port-80Codes
4-52
Revision
4-53
Error
Basic Input Output System BIOS
Error Message
4-54
4.7.2BMC Revision Level Identification
4.7Identifying BIOS and BMC Revision Levels
4.7.1BIOS Revision Level Identification
4.8.1Running the SCSI Utility
4.8.2Adaptec SCSI Utility Configuration Settings
4.8Adaptec SCSI Utility
User Setting
Basic Input Output System BIOS
Recommended Setting or
Revision
4.8.3Exiting Adaptec SCSI Utility
4-58
4-59
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Revision
Page
Revision
5.Jumpers and Connectors
Jumper and connector location key for Figure
5-61
5-62
I/O Back Panel location key for Figure
Figure 5-2.I/O Back Panel Connectors
5.1Jumper Blocks
5.1.1.1Clearing and Changing a Password
5.1.1.2Clearing CMOS
5-65
5.1.1.3Perfoming a BIOS Recovery Boot
Revision
5.1.2Setting Configuration Jumper Block 1L4
5.2Connectors
5.1.3Setting Configuration Jumper Block 6A
5.2.3I2C Power Connector P37
5.2.1Main ATX Power Connector P33
5.2.2Auxilary ATX Power Connector P34
Table 5-6.Main ATX Power Connector Pinout
5.2.6Speaker Connector P31
5.2.4System Fan Connectors P29, P27, P11
5.2.5Processor Connectors P12, P36
5.2.7Speaker Connector P25
Figure 5-3.Diskette Drive Connector Pin Diagram
5.2.8Diskette Drive Connector P20
5.2.9SVGA Video Port
Table 5-13.Diskette Drive Connector Pinout
5.2.12Serial Ports COM1 and COM2
5.2.10Keyboard and Mouse Connectors
5.2.11Parallel Port
Table 5-15.Keyboard and Mouse Connector Pinouts
Table 5-18. RJ-45LAN Connector Signals
5.2.13RJ-45LAN Connector
5.2.14USB Connectors
Table 5-19.USB Connectors
Table 5-20.Ultra SCSI Connector Pinout
5.2.15Ultra SCSI Connector P9
5.2.16Ultra160 SCSI Connector P8
Table 5-21.Ultra160 SCSI Connector
Table 5-22.IDE Connector Pinout
5.2.17IDE Connector P19
Figure 5-4.IDE Connector Pin Diagram
5-74
Revision
5.2.1832-BitPCI Connector
Table 5-23. 32-BitPCI Connector Pinout
5-75
5-76
5.2.1964-BitPCI Connector
Table 5-24. 64-BitPCI Connctor Pinout
Revision
5.2.20Front Panel 24-pinConnector Pinout P23
Table 5-25.Front Panel 24-pinConnector Pinout
5-77
5-78
Reserved
5-79
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Revision
Page
6.Power Consumption
6.1Calculated Power Consumption
STL2 Server Board TPS
6.2Measured Power Consumption
Power Consumption
Devices
7-83
7.Mechanical Specifications
Revision
7-84
Mechanical Specifications
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STL2 Server Board TPS
8.Regulatory and Integration Information
8.1Regulatory Compliance
8.2Installation Instructions
8.2.1Ensure EMC
8.2.2.1In Europe
8.2.3Prevent Power Supply Overload
8.2.4Place Battery Marking on Computer
8.2.2.2In the United States
8.2.5Use Only for Intended Applications
8.2.6Installation Precautions
8.3Environmental Limits
8.3.1System Office Environment
∙Humidity Non-Operating
8.3.2System Environmental Testing
∙Temperature Operating and Non-Operating
∙Shock Packaged and Unpackaged
Regulatory and Integration Information
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8-90
STL2 Server Board TPS
Glossary
Revision
Reference Documents
Index
Revision
See POST, 3-22, 3-24, 3-25, 4-29,4- 30, 4-33,
Revision