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Intel manual Revision September 22, Enterprise Platforms Group, STL2 Server Board

Models: STL2

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STL2 Server Board

Technical Product Specification

Revision 1.0

September 22, 2000

Enterprise Platforms Group

Page 1

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Intel manual Revision September 22, Enterprise Platforms Group, STL2 Server Board, Technical Product Specification

Contents

Technical Product Specification Revision September 22, Enterprise Platforms GroupSTL2 Server Board Disclaimers Revision HistoryRevision History STL2 Server Board TPSIntroduction Table of Contents2. STL2 Server Board Architecture Overview Server Management5. Jumpers and Connectors 4. Basic Input Output System BIOS4-29 5-61Mechanical Specifications Power Consumption6-81 7-83List of Figures List of Tables Table 4-26.POST Error Messages and Codes 1.Introduction 1.3STL2 Server Board Feature Overview1.1Purpose 1.2Audience1.4STL2 Server Board Block Diagram Figure 1-1.STL2 Server Board Block Diagram STL2 Server Board Block DiagramServerSet 3.0 LE STL2 Features BIOSIntroduction < This page intentionally left blank >STL2 Server Board TPS 2.1 Intel Pentium III Processor Subsystem 2.STL2 Server Board Architecture Overview2.1.1Supported Processor Types 2.1.3PGA370 Socket 2.1.2Dual Processor Operation2.1.5Termination Package 2.1.6APIC Bus2.3Memory 2.2ServerWorks ServerSet III LE Chipset∙NB6635 North Bridge 3.0LE ∙IB6566 South Bridge2.4.164-bit /66 MHz PCI Subsystem 2.4PCI I/O Subsystem2.4.1.1Ultra160 / Ultra WideSCSI Controller Revision 2.4.1.1.1AIC-7899Supported PCI Commands2.4.1.1.2SCSI Bus 2.4.232-bit/33MHz PCI Subsystem2.4.2.1Network Interface Controller NIC 2.4.2.1.1Supported Network Features 2.4.2.2Video Controller 2.4.2.2.1Video Controller PCI Signals2.4.2.2.3Video Modes 2.4.2.2.2Video Controller PCI CommandsTable 2-4.Video Controller Supported PCI Commands Table 2-5.Standard VGA Modes2.4.2.3.1PCI Interface 2.4.2.3IB6566 South Bridge2.4.2.3.2PCI Bus Master IDE Interface 2.5Chipset Support Components 2.4.2.6Power Management2.5.1Legacy I/O Super I/O National* PC97317VUL 2.4.2.3.3USB Interface2.5.1.7Power Management Controller 2.5.1.4Keyboard and Mouse Connectors2.5.1.1Serial Ports 2.5.1.2Parallel Port2.5.3External Device Connectors 2.5.2BIOS Flash2.6.1Default I/O APIC 2.6Interrupt RoutingSouth 2-18Interrupt Router2-19 Revision2.6.4Relationship between PCI IRQ and PCI Device 2.6.3PCI IdsTable 2-6.STL2 PCI IDs 2-21 RevisionSTL2 Server Board TPS STL2 Server Board Architecture OverviewPage 3.1Baseboard Management Controller 3.Server Management∙Monitors the event receiver 3.2Hardware Sensors∙Controls Wake-on-Lanvia Magic Packet* support 3-243-25 RevisionPlatform Security 3-263.3ACPI 3.5Wake On LAN Function 3.4AC Link Mode4.1BIOS Overview 4.Basic Input Output System BIOS4.1.2Flash Update Utility 4.1.1System BIOS4.1.2.1System Flash ROM Layout 4.2.1Configuration Utilities Overview 4.2Setup Utility4.2.2Setup Utility Operation 4.2.2.2Keyboard Command Bar 4.2.2.1Entering Setup UtilityEnter Execute Command F1 Help←→ Select Menu F9 Setup DefaultsF5/– Change Value F6/+ Change Value∙System Menu ∙Boot Menu ∙Exit Menu 4.2.2.4Main Menu SelectionsThese and associated submenus are described below Table 4-2.Main Menu SelectionsRevision Table 4-4.Processor Settings Submenu Selections4-35 Table 4-5.Advanced Menu Selections 4.2.2.5Advanced Menu Selections4-36 4-37 RevisionTable 4-9.Option ROM Submenu Selections Table 4-8.PCI Device Submenu SelectionsTable 4-10.Numlock Submenu Selections 4-38Table 4-11.Security Menu Selections 4.2.2.6Security Menu SelectionsRevision 4-39Table 4-12.Secure Mode Submenu Selections 4.2.2.7System Hardware Menu SelectionsTable 4-13.Server Menu Selections Table 4-14.Wake On Events Submenu SelectionsTable 4-16.Boot Menu Selections 4.2.2.8Boot Menu SelectionsTable 4-17.Boot Device Priority Selections Table 4-15.Console Redirection Submenu Selections4.2.2.9Exit Menu Selections 4.3CMOS Memory Definition4.5Flash Update Utility 4.4CMOS Default Override4.5.1Loading the System BIOS 4.5.2OEM Customization 4.5.2.1User-suppliedBIOS Code Support4-45 Revision# of bit available –1 Bit offset from start of CMOS of first bitBasic Input Output System BIOS 4.5.2.2Scan Point DefinitionsSTL2 Server Board TPS Scan Point4.5.3Language Area 4.5.4Recovery Mode4.5.2.3OEM Splash Screen 4.6.1POST Codes 4.6Error Messages and Error Codes∙Each group is made one-based1 through Table 4-24.Standard BIOS Port-80CodesExample Checkpoint 04Bh will be broken down to4-50 Configure advanced chipset registers4-51 RevisionTable 4-25.Recovery BIOS Port-80Codes 4.6.2POST Error Codes and MessagesTable 4-26.POST Error Messages and Codes 4-524-53 RevisionError Message Basic Input Output System BIOSError 4-544.7.1BIOS Revision Level Identification 4.7Identifying BIOS and BMC Revision Levels4.7.2BMC Revision Level Identification 4.8Adaptec SCSI Utility 4.8.2Adaptec SCSI Utility Configuration Settings4.8.1Running the SCSI Utility Recommended Setting or Basic Input Output System BIOSUser Setting Revision4-58 4.8.3Exiting Adaptec SCSI UtilityRevision < This page intentionally left blank >4-59 Page Jumper and connector location key for Figure 5.Jumpers and ConnectorsRevision 5-61Figure 5-2.I/O Back Panel Connectors I/O Back Panel location key for Figure5-62 5.1Jumper Blocks 5.1.1.2Clearing CMOS 5.1.1.1Clearing and Changing a PasswordRevision 5.1.1.3Perfoming a BIOS Recovery Boot5-65 5.1.2Setting Configuration Jumper Block 1L4 5.1.3Setting Configuration Jumper Block 6A 5.2Connectors5.2.2Auxilary ATX Power Connector P34 5.2.1Main ATX Power Connector P335.2.3I2C Power Connector P37 Table 5-6.Main ATX Power Connector Pinout5.2.5Processor Connectors P12, P36 5.2.4System Fan Connectors P29, P27, P115.2.6Speaker Connector P31 5.2.7Speaker Connector P255.2.9SVGA Video Port 5.2.8Diskette Drive Connector P20Figure 5-3.Diskette Drive Connector Pin Diagram Table 5-13.Diskette Drive Connector Pinout5.2.11Parallel Port 5.2.10Keyboard and Mouse Connectors5.2.12Serial Ports COM1 and COM2 Table 5-15.Keyboard and Mouse Connector Pinouts5.2.14USB Connectors 5.2.13RJ-45LAN ConnectorTable 5-18. RJ-45LAN Connector Signals Table 5-19.USB Connectors5.2.16Ultra160 SCSI Connector P8 5.2.15Ultra SCSI Connector P9Table 5-20.Ultra SCSI Connector Pinout Table 5-21.Ultra160 SCSI ConnectorFigure 5-4.IDE Connector Pin Diagram 5.2.17IDE Connector P19Table 5-22.IDE Connector Pinout 5-74Table 5-23. 32-BitPCI Connector Pinout 5.2.1832-BitPCI ConnectorRevision 5-75Table 5-24. 64-BitPCI Connctor Pinout 5.2.1964-BitPCI Connector5-76 Table 5-25.Front Panel 24-pinConnector Pinout 5.2.20Front Panel 24-pinConnector Pinout P23Revision 5-77Reserved 5-78Revision < This page intentionally left blank >5-79 Page 6.1Calculated Power Consumption 6.Power ConsumptionPower Consumption 6.2Measured Power ConsumptionSTL2 Server Board TPS DevicesRevision 7.Mechanical Specifications7-83 < This page intentionally left blank > Mechanical Specifications7-84 STL2 Server Board TPS8.1Regulatory Compliance 8.Regulatory and Integration Information8.2.1Ensure EMC 8.2Installation Instructions8.2.4Place Battery Marking on Computer 8.2.3Prevent Power Supply Overload8.2.2.1In Europe 8.2.2.2In the United States8.3Environmental Limits 8.2.6Installation Precautions8.2.5Use Only for Intended Applications 8.3.1System Office Environment∙Temperature Operating and Non-Operating 8.3.2System Environmental Testing∙Humidity Non-Operating ∙Shock Packaged and Unpackaged8-90 < This page intentionally left blank >Regulatory and Integration Information STL2 Server Board TPSRevision GlossaryReference Documents Revision IndexSee POST, 3-22, 3-24, 3-25, 4-29,4- 30, 4-33, Revision